Fuji Electric Co., Ltd.

Sumitomo Electric Industries, Limited

National Institute of Advanced Industrial Science and Technology

Akimasa Kinoshita

Yasuhiko Oonishi

Yasuyuki Hoshi

Yuichi Harada

Takashi Tsuji

Shinsuke Harada

Kenji Fukuda

Keiji Okumura

Yasunori Tanaka

Masanobu Iwaya

Yusuke Kobayashi

Noriyuki Iwamuro

Makoto Utsumi

Shingo Hayashi

Mina Ryo

Hiroyuki Fujisawa

Hiromu Shiomi

Masahito Otsuki

Takeshi Tawara

Shinya Kyogoku

Fumikazu Imai

Yoshiyuki Sakai

Shinichi Nakamata

Yoshihito Ichikawa

In an edge termination region, a FLR structure configured by FLRs having a floating potential and surrounding concentrically a periphery of an active region is provided. The FLR structure is divided into at least two FLR segments with a predetermined FLR as a boundary. An n-th interval between an adjacent two of the FLRs is wider than a first interval between a p-type extension portion and the FLR closest to a chip center (n=2 to total number of the FLRs). The n-th interval between an adjacent two of the FLRs increases in arithmetic progression the closer the adjacent two are to a chip end, the n-th interval increasing in arithmetic progression by a corresponding one of constant increase increments respectively corresponding to the FLR segments; the closer a FLR segment is to the chip end, the wider is the constant increase increment corresponding thereto.

Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device

A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an insulating film, first electrodes, a second electrode, and trenches. The first semiconductor regions and the second semiconductor regions are periodically disposed apart from one another in a first direction in which the trenches extend in a stripe pattern.

Silicon carbide semiconductor device

A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, a gate insulating film, gate electrodes, first electrodes, a second electrode, and a gate pad portion configured by a gate electrode pad and a connecting portion. The second semiconductor layer includes a first region facing the connecting portion and a second region facing a corner portion of the gate electrode pad, and the first and second regions are free of the second semiconductor regions. The oxide film is provided on surfaces of the second semiconductor regions and the first and second regions, and the oxide film and the gate insulating film are made of a same material.

A voltage withstanding structure disposed in an edge termination region is a spatial modulation junction termination extension (JTE) structure formed by a combination of a JTE structure and a field limiting ring (FLR) structure. All FLRs configuring the FLR structure are surrounded by an innermost one of p-type regions configuring the JTE structure. An innermost one of the FLRs is disposed overlapping a p-type extension and the innermost one of the p-type regions, at a position overlapping a border between the p-type extension and the innermost one of the p-type regions. The FLRs are formed concurrently with p-type contact regions in an active region and have an impurity concentration substantially equal to an impurity concentration of the p-type contact regions. An n-type channel stopper region is formed concurrently with n-type source regions in the active region and has an impurity concentration substantially equal to an impurity concentration the n-type source regions.

A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, first base regions of a second conductivity type, second base regions of the second conductivity type, a second semiconductor layer of the second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, and trenches. Between adjacent first base regions, at least two of the trenches, at least two of the gate electrodes, and at least two of the second base regions are disposed, the second base regions disposed between the adjacent first base regions being disposed separate from one another and separate from the first base regions, in a direction in which the trenches are arranged.

Semiconductor device

In a silicon carbide semiconductor device and a silicon carbide semiconductor circuit device equipped with the silicon carbide semiconductor device, a gate leak current that flows when negative voltage with respect to the potential of a source electrode is applied to the gate electrode is limited to less than 2&#xd7;10A and the gate leak current is limited to less than 3.7&#xd7;10A/m.

Silicon carbide semiconductor device and silicon carbide semiconductor circuit device

A method of manufacturing an insulated gate semiconductor device includes simultaneously forming a gate trench and a contact trench that respectively penetrate form a top of the electrode contact region through a main electrode contact region and a injection control region in a depth direction and respectively reach a charge transport region, the contact trench being disposed at a position laterally separated from the gate trench in a plan view; and embedding a gate electrode inside the gate trench with a gate insulating film interposed therebetween, thereby forming an insulated gate structure, and simultaneously embedding an injection suppression region inside the contact trench, the gate electrode and the injection suppression region being both made of a second semiconductor material having a narrower bandgap than a bandgap of the first semiconductor material of the charge transport region.

Method of manufacturing insulated gate semiconductor device with injection suppression structure

First p-type regions are provided directly beneath trenches, separate from a p-type base region and facing bottoms of the trenches in a depth direction. The first p-type regions are exposed at the bottoms of the trenches and are in contact with a gate insulating film at the bottoms of the trenches. Second p-type regions are each provided between (mesa region) adjacent trenches, separate from the first p-type regions and the trenches. Drain-side edges of the second p-type regions are positioned closer to a source side than are drain-side edges of the first p-type regions. In each mesa region, an n-type region is provided separate from the first p-type regions and the trenches. The n-type regions are adjacent to and face the second p-type regions in the depth direction.

A semiconductor device, including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided on the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at a surface thereof, a plurality of gate insulating films in contact with the second semiconductor layer, a plurality of gate electrodes respectively provided on the gate insulating films, a plurality of first electrodes provided on the second semiconductor layer and the first semiconductor regions, and a second electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate contains boron, a concentration of the boron therein being in a range from 5&#xd7;10/cmto 5&#xd7;10/cm.

A semiconductor device includes an active region through which a main current passes during an ON state. In the active region, the semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, gate insulating films, gate electrodes, an interlayer insulating film, first electrodes, a second electrode, first trenches, a second trench, a polycrystalline silicon layer provided in the second trench via one of the gate insulating films, and a silicide layer selectively provided in a surface layer of the polycrystalline silicon layer. The polycrystalline silicon layer and the silicide layer are electrically connected with the gate electrodes.

An insulated-gate semiconductor device includes: an n-type current spreading layer disposed on an n-type drift layer; a p-type base region disposed on the current spreading layer; a n-type main-electrode region arranged in an upper portion of the base region; an insulated-gate electrode structure provided in a trench; and a p-type gate-bottom protection-region being in contact with a bottom of the trench, including a plurality of openings through which a part of the current spreading layer penetrates, being selectively buried in the current spreading layer, wherein positions of the openings cut on both sides of a central line of the trench are shifted from each other about the central line in a longitudinal direction of the trench in a planar pattern.

Insulated-gate semiconductor device and method of manufacturing the same

A semiconductor device includes an N-type silicon carbide layer, a P-type region, an N-type source region, a P-type contact region, a gate insulating film, a gate electrode, and a source electrode on the front surface side of an N-type silicon carbide substrate. A drain electrode is located on the back surface of the N-type silicon carbide substrate. A life time killer introduction region is located along an entire interface of the N-type silicon carbide layer and the bottom face of the P-type region. The life time killer is introduced by implanting helium or protons from the back surface side of the N-type silicon carbide substrate after forming a surface structure of an element on the front surface side of the N-type silicon carbide substrate and before forming the drain electrode.

Semiconductor device and method of manufacturing semiconductor device

A gate pad includes a first portion disposed in a gate pad region and a second portion continuous with the first portion and disposed in a gate resistance region. The gate pad has a planar shape in which the second portion protrudes from the first portion. A gate polysilicon layer provided on a front surface of a semiconductor substrate via a gate insulating film is disposed between the semiconductor substrate and an interlayer insulating film, has a surface area that is at least equal to a surface area of the gate pad, and faces the gate pad in a depth direction. The gate polysilicon layer has a planar outline similar to that of the gate pad and includes continuous first and second portions, the first portion facing the first portion of the gate pad overall, and a second portion facing the second portion of the gate pad.

A trench gate MOSFET has at an n-type current spreading region between an n-type drift region and a p-type base region, a first p-type region facing a bottom of a trench, and a second p-type region disposed between adjacent trenches. The first and the second p-type regions extend parallel to a first direction in which the trench extends and are partially connected by a p-type connecting portion and thus, disposed in a ladder shape when viewed from the front surface of a semiconductor substrate. The second p-type region has at a portion of a surface on a drain side, a recessed portion that is recessed toward a source side. One or more recessed portions is provided between connection sites in the second p-type region for connection with the p-type connecting portions that are adjacent to each other in the first direction X.

Growing community of inventors

Matsumoto, Japan

Akimasa Kinoshita