International Business Machines Corporation

Akihisa Sekiguchi

Toshiharu Furukawa

David V Horak

Oleg Gluschenkov

Michael Patrick Chudzik

Anthony I-Chih Chou

Bruce Bennett Doris

Jeffrey W Sleight

Mark Charles Hakey

Lee Chen

Anthony I Chou

Dae-Gyu Park

Wesley Charles Natzle

Patrick Ronald Varekamp

Wenjuan Zhu

Sadanand Vinayak Deshpande

Katsunori Onishi

Qingyun Yang

Len Yuan Tsou

Roland Germann

Paul Daniel Kirsch

Byoung Hun Lee

Kristen Scheer

Dragan Podlesnik

Heemyoung Park

A semiconductor structure and method of forming the same, comprising forming a uniform buffer layer of diffusion-controlling stable material on top of a base gate dielectric layer, and then forming a uniform layer which contains a source of transitional metal atoms, and then annealing the structure to diffuse the transitional metal atoms from their source through the diffusion-controlling material and into the base gate dielectric layer.

Method of forming an ultra-thin [[HfSiO]] metal silicate film for high performance CMOS applications and semiconductor structure formed in said method

A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed round the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion regions.

Formation of a disposable spacer to post dope a gate conductor

Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.

Forming gate oxides having multiple thicknesses

A method of forming a structure having sub-lithographic dimensions is provided. The method includes: forming a chamfered mandrel on a substrate, the mandrel having an angled surface; and performing an angled ion implantation to obtain an implanted shadow region in the substrate, the implanted shadow mask having at least one sub-lithographic dimension.

Method of making sub-lithographic features

The present invention provides a cost effective and simple method of forming isolation regions, such as shallow trench isolation regions, in a semiconductor substrate that avoids etching into the trench. In the present invention, the isolation regions are formed by utilizing a selective ion implantation process that creates an oxygen implant region near the upper surface of the substrate. Upon a subsequent anneal step, the oxygen implant region is converted into an isolation region that has an upper surface that is substantially coplanar with the upper surface of the substrate.

Method of fabricating shallow trench isolation by ultra-thin SIMOX processing

A method of forming CMOS semiconductor materials with PFET and NFET areas formed on a semiconductor substrate, covered respectively with a PFET and NFET gate dielectric layers composed of silicon oxide and different degrees of nitridation thereof. Provide a silicon substrate with a PFET area and an NFET area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric layer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer and the PFET gate dielectric layer can have the same thickness.

Method for separately optimizing thin gate dielectric of PMOS and NMOS transistors within the same semiconductor chip and device manufactured thereby

An apparatus for self-aligning an optical fiber to an optical waveguide. The apparatus includes an optical waveguide chip including: one or more optical waveguides formed on a first substrate, each optical waveguide having a protruding portion; and one or more alignment rails formed on the first substrate, each alignment rail spaced apart from each optical waveguide by a predetermined distance; and an alignment jig including: one or more grooves formed in a second substrate, each groove adapted to receive one protruding portion and each groove supporting one optical fiber in alignment with one optical waveguide; and one or more alignment grooves formed on the second substrate, each alignment groove spaced apart from the grooves by the predetermined distance and adapted to mate with the alignment rails.

Self-aligned optical waveguide to optical fiber connection system

A method of selectively forming either an epi-Si-containing or a silicide layer on portions of a Si-containing substrate wherein a nitrogen-containing layer formed by a low-temperature nitridation process is employed to prevent formation of the epi-Si-containing or silicide layer in predetermined areas of the substrate. The method of the present invention includes the steps of subjecting at least one exposed surface of a Si-containing substrate to a low- temperature nitridation process so as to form a nitrogen-containing layer at or near the at least one exposed surface, wherein other surfaces of the Si-containing substrate are protected by a patterned photoresist; removing the patterned photoresist from the other surfaces of the Si-containing substrate; and forming an epi-Si-containing layer or a silicide layer on the other surfaces of the substrate which do not contain the nitrogen-containing layer. In accordance with the present invention, epi-Si-containing or silicide is not formed in areas containing the nitrogen-containing layer.

Patterned plasma nitridation for selective epi and silicide formation

The discovery that a location exists in a plasma sheath surrounding a plasma near a plasma confining surface where recombination of ions and electrons is favored due to Coulombic interaction is exploited to provide filtration of flux components and enhance neutralization of ions extracted from the plasma. By engineering of the dimensions of apertures in an apertured plate in accordance with plasma conditions and differential pumping, a high quality, high flux neutral beam can be developed wherein the particle energies may be scalable from very low levels below that which causes crystal lattice damage in semiconductor materials to very high levels. The production of a beam of neutral beam of good directivity and well-defined geometry is further exploited to provide predictability in plasma chemistry reactions and to form reactants in-situ for semiconductor processing. In-situ production of minute quantities of hydrofluoric acid for interface tailoring provides a 'dry', high vacuum compatible alternative to wet etch processes.

Growing community of inventors

Briarcliff Manor, NY, United States of America

Akihisa Sekiguchi