Hitachi, Ltd.

Akihiro Tomozawa

Toshio Sasaki

Yoshio Sakai

Toshiaki Masuhara

Osamu Minato

Akira Kikuchi

Hisao Katto

Takashi Yamaguchi

Norikazu Hashimoto

Shin-ichi Muramatsu

Norio Anzai

Kensuke Nakata

Takanori Nishimura

Akira Nagase

Masayasu Tsunematsu

Takashi Agastuma

A semiconductor device including at least a resistance element formed of polycrystalline silicon having a high resistivity. An electrode is provided on the high resistance polycrystalline silicon region with a silicon dioxide film and a silicon nitride film being interposed therebetween. The electrode is coupled to the ground potential. In this manner, high stability is obtained in the behavior of the resistance element inasmuch as the formation of a parasitic MOS device under said high resistance region is suppressed, and the threshold voltage of any such MOS device is made raised.

Semiconductor device

In order to prevent the formation of a parasitic PNPN thyristor in an integrated circuit having at least one NPN transistor, a layer of semiconductor material of a conductivity type opposite that of the substrate is formed on the substrate. An isolation region of the same conductivity type as the substrate is formed on this layer and a further layer of the same conductivity type as the isolation region, but of a higher impurity concentration, is formed on the back surface of the substrate. A diffusion layer of the same conductivity type as the substrate, which serves as the base region of the NPN transistor, is formed on the layer having the conductivity type opposite to that of the substrate. A further layer of the same conductivity type and a higher impurity concentration than the isolation region is formed on the back surface of the substrate and an insolation layer is formed on the back surface of the substrate and on the substrate. A further diffusion layer of a conductivity type opposite to that of the substrate, which serves as the emitter region of the transistor is formed using the insolation layer as a mask.

Method of making integrated circuits free from the formation of a

A method of producing an MIS structure having self-alignment construction, wherein an insulating film is formed on the surface of a semiconductor substrate, a semiconductor layer is formed on a selected area of the insulating film, parts of the insulating film are etched using the semiconductor layer as a mask, and the surface of the semiconductor layer is etched in such manner that the underlying insulating film may not be etched, whereby the marginal portion of the semiconductor layer which otherwise projects laterally beyond the underlying insulating film is caused to recede.

Method of producing MIS structure

A method for forming an insulating film on an interconnection layer for an integrated circuit, or the like, includes the steps of forming an aluminum layer on the surface of a substrate, oxidizing a thin portion of the upper surface of the aluminum layer in order to convert the thin parts into a porous alumina film, applying a photoresist film having a predetermined pattern on the upper surface of the porous alumina film, and etching those portions of the porous alumina film, together with the aluminum layer which are not covered with the photoresist film. Then, the photoresist film is removed and an aluminum film is formed on the entire surface of the resulting substrate; the aluminum film is oxidized, to form a porous alumina film, and the surface of the remaining aluminum layer is anodized, in order to form a non-porous alumina film. Finally, unnecessary portions of the remaining porous alumina film are removed, and a film is formed by chemical vapor deposition on the resulting structure.

Method of forming insulating film on interconnection layer

Growing community of inventors

Kodaira, Japan

Akihiro Tomozawa