Kabushiki Kaisha Toshiba

Akihiro Mishima

Yoichi Suzuki

Masami Masuda

Makoto Segawa

Yasumitsu Nozawa

Yasuo Naruke

Mitsuhiko Kosakai

An improved semiconductor memory device capable of easily detecting the location of a defective bit line and a defective memory cell as a leakage current path for a short time is provided. A region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first large region and a remaining second large region, either of said first and second large regions being selected by simultaneously selecting a predetermined number of said column selection lines. Then, a region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first small region and a remaining second small region, said first and second small regions constituting said one of the first and second large regions, either of said first and second small regions being selected by simultaneously selecting a predetermined number of said column selection lines. For this purpose, an address signal output control circuit is provided within the semiconductor memory device. The address signal output control circuit is supplied with an address output control signal as externally given as a control signal for the purpose of selecting said row selection line by taking control of said row addressing signal in order to perform the control process as described above.

Semiconductor memory device implemented with a test circuit

A semiconductor memory device includes bit lines and word lines arranged lengthwise and breadthwise, memory cells 1 capable of reading out and writing in, MOS transistors Q1 and Q2 for pre-charge, MOS transistors Q3 for short-circuiting, and transistors Q4 and Q5 for setting voltage level. The bit lines are provided two pieces at each bit. Between the MOS transistors Q1, Q2 for pre-charge and the bit lines driving power supply terminal Vcc, three pieces of the fuses F1-F3 are connected at each column. When the leak defect occurs to the bit lines, all of the fuses F1-F3 connected to the bit lines are cut. Further, a semiconductor memory device includes a plurality of section regions, a redundancy circuit RD1 which replaces a defective cell at each section region, a redundancy circuit RD2 which replaces the defective cell at each row address. The section regions are provided at each address in the column direction. In each section region, cell ground power supply lines Vss are formed circularly. Outside each section region a pad ground power supply line Vss' are formed. Each of the cell ground power supply lines Vss and the pad ground power supply line Vss' are connected via a plurality of fuses F connected in parallel.

Semiconductor memory device and method relieving defect of semiconductor

Growing community of inventors

Kanagawa-ken, Japan

Akihiro Mishima