Fuji Electric Co., Ltd.

Fuji Electric Holdings Co., Ltd.

Akihiko Ohi

Takeyoshi Nishimura

Hiroshi Kimura

Hitoshi Sumida

Kazuo Mukae

Toshiyuki Matsui

Hiroyuki Tanaka

Takeshi Suzuki

Chun-Wai Ng

Yoshiaki Toyada

Kin-On Sin

Shoji Kitamura

Takashi Ishii

Koichi Tsuda

Katsunori Suzuki

Yoshihiko Nagayasu

Daisuke Kishimoto

Hitoshi Kuribayashi

Takahiro Ooyama

Yuji Sano

A mask used to form an nsource layer () is formed by a nitride film on the surface of a substrate before a trench () is formed. At this time, a sufficient width of the nsource layer () on the surface of the substrate is secured. Thereby, stable contact between the nsource layer () and a source electrode () is obtained. A CVD oxide film () that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode () embedded in the trench (), and non-doped poly-silicon () that is not oxidized is formed on the CVD oxide film (). Thereby, generation of void in the CVD oxide film () is suppressed and, by not oxidizing the non-doped poly-silicon (), a semiconductor apparatus is easily manufactured.

MOS-driven semiconductor device and method for manufacturing MOS-driven semiconductor device

A fault position analysis method and a fault position analysis device for a semiconductor device, through which a fault position of a SiC semiconductor device can be analyzed and specified by an OBIRCH method, are disclosed. The fault position analysis method for the semiconductor device scans and irradiates a device and a circuit on a front surface of a substrate with a laser beam from a rear surface side of the substrate of the semiconductor device to heat the device and the circuit. It causes a current to flow to the device and the circuit while being heated, detects a change in a resistance value caused by a change in a current, and analyzes the fault position. The semiconductor device is a semiconductor device which uses an N-doped SiC substrate. Laser beams having wavelengths of 650 to 810 nm are used.

Fault position analysis method and fault position analysis device for semiconductor device

A method of manufacturing a super-junction semiconductor device facilitates increasing the epitaxial growth rate without increasing the manufacturing steps greatly. In substitution for the formation of alignment mark in the surfaces of the second and subsequent non-doped epitaxial layers, patterning for forming a new alignment mark is conducted simultaneously with the resist pattering for selective ion-implantation into the second and subsequent non-doped epitaxial layers in order to form the new alignment mark at a position different from the position, at which the initial alignment mark is formed, and to form the new alignment mark in every one or more repeated epitaxial layer growth cycles.

Method of manufacturing super-junction semiconductor device

In the method for manufacturing a semiconductor device according to the invention including the step of forming trenches having the depth thereof in perpendicular to the major surface of a semiconductor substrate, the step of forming trenches includes the steps of performing trench etching using an insulator film, formed on the major surface of the semiconductor substrate and shaped with a predetermined pattern, for a mask to form the trenches; etching the inside of the trenches using a halogen containing gas to smoothen the inside of the trenches; and thermally treating in a non-oxidizing and non-nitriding atmosphere. The manufacturing method according to the invention facilitates well removing the etching residues remaining in the trenches and rounding the trench corners properly when the trenches are 2 &#x3bc;m or narrower in width and even when the trenches are 1 &#x3bc;m or narrower in width.

Method for manufacturing a semiconductor device having trenches defined in the substrate surface

A superconducting transistor having a source region and a drain region are formed by a YBCO film on a barrier layer, which is composed of a PBCO film formed on an STO substrate. A gate electrode is disposed on the thinner wall at the back of the STO substrate. In a superconducting transistor so constructed the electric field created by the gate voltage works effectively at an interface with the barrier layer, more carriers can be drawn out relative to the applied gate voltage, and it becomes possible for a large superconduction current to flow.

Superconducting device structure with Pr-Ba-Cu-O barrier layer

A superconducting transistor with superior withstand voltage having source region and a drain region formed of oxide superconductors 3, a PrBa.sub.2 Cu.sub.3 O.sub.7-x layer 2 or an ScBa.sub.2 Cu.sub.3 O.sub.7-x layer 2 forming an intermediate region sandwiched by the source and drain regions. The regions are disposed on a substrate 1. An insulation layer 4 is disposed on the intermediate region. A transistor uses the intermediate region as an insulator when the gate is turned off, and as a superconductor when the gate is turned on.

Superconducting FET with Pr-Ba-Cu-O channel

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Nagano, Japan

Akihiko Ohi