Intel Corporation

Other

Akhilesh Kumar

Manoj Khare

Lily Pao Looi

Ioannis T Schoinas

Mani Ayyar

Eric R Delano

Phanindra Mannava

Jose Andy Vargas

Doddaballapur N Jayasimha

Kenneth C Creta

Ching-Tsun Chou

Mani Azimi

Faye A Briggs

Dongkook Park

Jay Jayasimha

Sujoy Sen

Murugasamy K Nachimuthu

Srinivas Chennupaty

Victor W Lee

Kai Cheng

Naveen Cherukuri

Sin Sim Tan

Suresh S Chittor

Kiran A Padwekar

Donglai Dai

Seungjoon Park

Rajee S Ram

Aniruddha Vaidya

Srinand Venkatesan

Andalib Khan

Sanjay Dabral

Robert T George

Anahita Shayesteh

Dennis W Brzezinski

Michel P Cekleov

Rama R Menon

Surhud Khare

Hariharan L Thantry

Ken Creta

Ioannis Yannis Schoinas

Doddaballapur Narasimha-Murthy Jayasimha

Livio B Soares

Neha Gholkar

Doddabaliapur Narasimha-Murthy Jayasimha

Livio Soares

Disclosed embodiments relate to a cache line eviction algorithm. In one example, a system includes a last level cache (LLC) having multiple ways, each allocated to one of multiple priorities, each having specified minimum and maximum ways to occupy, a cache control circuit (CCC) to store an incoming cache line (CL) having a requestor priority to an invalid CL, if any, otherwise, when the requestor priority is a lowest priority and has an occupancy of one or more, or when the occupancy is at a maximum, to evict a least recently used (LRU) CL of the requestor priority, otherwise, when the occupancy is between a minimum and a maximum, to evict a LRU CL of the requestor or a lower priority, otherwise, when the occupancy is less than the minimum, to evict a LRU CL, if any, of the lower priority, and otherwise, to evict a LRU CL of a higher priority.

Flexible cache allocation technology priority-based cache line eviction algorithm

Techniques and mechanisms for interconnecting network circuitry of an integrated circuit (IC) die and physical layer (PHY) circuits of the same IC die. In an embodiment, nodes of the network circuitry include first routers and processor cores, where the first routers are coupled to one another in an array configuration which includes rows and columns. First interconnects each extend to couple both to a corresponding one of the PHY circuits and to a corresponding one of the first routers. For each of one or more of the first interconnects, a respective one or more rows (or one or more columns) of the array configuration extend between the corresponding PHY and the corresponding router. In another embodiment, the network circuitry comprises network clusters which each include a different respective row of the array configuration.

Device, system and method for coupling a network-on-chip with PHY circuitry

Techniques for power gating. A first on-die router has an output port to receive data from a switching fabric. The output port is placed in a power-gated state if there is no activity in the output port for a current cycle and no messages are to be received by the output port during a subsequent cycle. A second on-die router has an input port coupled with the output port of the first on-die router. The input port is placed in a power-gated state if an input port buffer is empty and the output port is not active. Power-gating of the input port and the output port are independent of each other.

Reduced wake up delay for on-die routers

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Method, system, and apparatus for dynamic reconfiguration of resources

Layout-aware modular decoupled crossbar and router for on-chip interconnects and associated micro-architectures and methods of operation. A crossbar and router architecture called MoDe-X (Modular Decoupled Crossbar) is disclosed that supports 5-port routing for use in 2D mesh interconnects and is implemented through use of decoupled row and column sub-crossbar modules in combination with feeder wiring and control logic that enables routing between ports on the row and column sub-crossbar modules. The corresponding MoDe-X router supports 5-port routing between various router input and output port combinations while reducing both router area and power consumption when compared with a conventional 5&#xd7;5 crossbar design and implementation. The MoDe-X micro-architecture can be configured to support both single and dual local port injection configurations.

Modular decoupled crossbar for on-chip router

In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed.

Region based technique for accurately predicting memory accesses

In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed.

Replacing cache lines in a cache memory based at least in part on cache coherency state information

Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.

Method, system, and apparatus for system level initialization by conveying capabilities and identifiers of components

In one embodiment, the present invention includes a directory to aid in maintaining control of a cache coherency protocol. The directory can be coupled to multiple caching agents via an interconnect, and be configured to store a entries associated with cache lines. The directory also includes logic to determine a time delay before the directory can send a concurrent snoop request. Other embodiments are described and claimed.

Optimizing concurrent accesses in a directory-based coherency protocol

Methods and apparatus relating to a fairness mechanism for starvation prevention in directory-based cache coherence protocols are described. In one embodiment, negatively-acknowledged (nack'ed) requests from a home agent may be tracked (e.g., using distributed linked-lists). In turn, the tracked requests may be served in a fair order. Other embodiments are also disclosed.

Fairness mechanism for starvation prevention in directory-based cache coherence protocols

Growing community of inventors

Sunnyvale, CA, United States of America

Akhilesh Kumar