Texas Instruments Corporation

Ajith Varghese

Hiroaki Niimi

Husam N Alshareef

Narendra Singh Mehta

Rajesh B Khamankar

Jarvis Benjamin Jacobs

Wayne A Bather

Haowen Bu

James Joseph Chambers

Angelo Pinto

Shaofeng Yu

Shashank Sureshchandra Ekbote

Lindsey H Hall

Malcolm John Bevan

Reima Tapani Laaksonen

Anand T Krishnan

Borna J Obradovic

Craig Henry Huffman

Cathy A Chancellor

Benjamin Moser

Terrence J Riley

Jonathan McAulay Holt

A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

Transistor performance using a two-step damage anneal

Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics.

Mitigation of gate to contact capacitance in CMOS flow

Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.

Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates

A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolation trench, which exhibits a five-fold greater resistance to nitride etching solutions as compared with DCS nitride, thereby allowing protection against damage from unintended over-etching. The bis-(t-butylamino)silane-based nitride layer also exerts a greater tensile strain on moat regions that results in heightened carrier mobility of active regions, thereby increasing the performance of NMOS transistors embedded therein.

Highly selective liners for semiconductor fabrication

A method for preventing oxidation in a high-k dielectric/metal gate stack in the manufacture of an integrated circuit device is disclosed. In a detailed embodiment, a PMOS region stack has nitrided hafnium silicide, tungsten, tantalum nitride and polysilicon layers. An NMOS region stack has nitrided hafnium silicide, tungsten silicide, tantalum nitride and polysilicon layers. A thin polysilicon layer deposited over the stacks is converted to an oxide using a low temperature ultraviolet ozone oxidation process or a plasma nitridation using decoupled plasma nitridation or NHannealing. The oxide provides a coating over the top and sides of the stacks to protect metal and interfaces from oxidation.

Low temperature polysilicon oxide process for high-K dielectric/metal gate stack

A method of manufacturing a semiconductor device including calibrating an ion implant process. The calibration includes forming a dielectric layer over a calibration substrate. A dopant is implanted into the dielectric layer. Charge is deposited on a surface of the dielectric layer, and voltage on the surface is measured. An electrical characteristic of the dielectric layer is determined, and a doping level of the dielectric layer is determined from the electrical characteristic. The electrical characteristic is associated with an operating set-point of the ion implant process. The calibrated ion implant process is used to implant the dopant into a semiconductor substrate.

Semiconductor device manufactured using a non-contact implant metrology

A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.

Thermal treatment of nitrided oxide to improve negative bias thermal instability

The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device () having a first gate dielectric layer () and a first gate electrode layer () located over a substrate (), wherein the first gate dielectric layer () has an amount of nitrogen located therein. In addition to the PMOS device (), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device () having a second gate dielectric layer () and a second gate electrode layer () located over the substrate (), wherein the second gate dielectric layer () has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device () and the NMOS device ().

CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers

The present invention, in one aspect, provides a method of manufacturing a microelectronics devicethat includes depositing a first gate dielectric layerover a substrate, subjecting the first gate dielectric layerto a first nitridation process, forming a second gate dielectric layerover the substrateand having a thickness less than a thickness of the first gate dielectric layer, and subjecting the first and second gate dielectric layersto a second nitridation process, wherein the first and second nitridation processes are different. The present invention also provides a microelectronics devicefabricated in accordance with the method.

Method to obtain uniform nitrogen profile in gate dielectrics

A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer is patterned and trench regions are formed using the hard mask layer as a mask. An oxide trench liner that induces compressive strain into active regions of the PMOS region is formed within trench regions of the PMOS region. A nitride trench liner that induces tensile strain into active regions of the NMOS region is formed within the NMOS trench regions.

Methods of improving drive currents by employing strain inducing STI liners

A method forms a semiconductor device comprising a modifiable strain inducing layer. A semiconductor body is provided. First and second regions of the semiconductor body are identified. A modifiable tensile strain inducing layer is formed over the device within the first and second regions. A mask is then formed that exposes the second region and covers the first region. A material is selected for a modification implant and the selected material is implanted into the second region thereby converting a portion of the modifiable tensile strain inducing layer into a compressive strain inducing layer within the PMOS region.

Strain modulation employing process techniques for CMOS technologies

The present invention is generally directed towards a method for removing hydrocarbon contamination from a substrate prior to a nitridation step, therein providing for a generally uniform nitridation of the substrate. The method comprises placing the substrate in a process chamber and flowing an oxygen-source gas into the process chamber. A first plasma is formed in the process chamber for a first predetermined amount of time, wherein the hydrocarbons combine with one or more species of the oxygen-source gas in radical form to form product gases. The gases are removed from the process chamber and a nitrogen-source gas is flowed into the process chamber. A second plasma is then formed in the process chamber for a second predetermined amount of time, therein nitriding the substrate in a significantly uniform manner.

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McKinney, TX, United States of America

Ajith Varghese