Alliance Semiconductor Corporation

Lara Technology, Inc.

Other

Ajit K Medhekar

Chitranjan N Reddy

Michael C Stephens, Jr

Jayan R Ramankutty

James G Washburn

Eric Voelkel

A modified binary content addressable memory (CAM) (,) having a fast variable prefix matching capability is disclosed. The modified CAM (,) includes modified CAM cells (,(,) to,(n,m)), each of which includes a store/compare circuit (,(,) to,(n,m)) for storing a data value and comparing the data value to a comparand value. In addition, each modified CAM cell (,(,) to,(n,m)) further includes a multiplexer (MUX) circuit (,(,) to,(n,m)). Each MUX circuit (,(,) to,(n,m)) receives a non-shifted comparand value from a modified CAM cell of a previous row and same column, and a shifted comparand value from a modified CAM cell of the previous row and an adjacent column. The MUX circuits (,(,) to,(n,m)) enable a comparand value to be shifted as it is applied to consecutive data values.

Enhanced binary content addressable memory for longest prefix address matching

A ternary content addressable memory (CAM) (800) having a massive, parallel shift capability is disclosed. The CAM (800) includes an array of CAM cells (802(1,1) to 802(1,4)), each of which includes a data value register (804(1,1) to 804(1,4)) and a mask value register (806(1,1) to 806(1,4)). To enable parallel shifting between a CAM cell in one row with a corresponding CAM cell in a higher row, each data value register (804(1,1) 804(1,4)) and mask value register (806(1,1) to 806(1,4)) includes an upper data input (UD) coupled the output of a CAM cell in the higher row. To enable parallel shifting between a CAM cell in one row with a corresponding CAM cell in a lower row, each data value register (804(1,1) 804(1,4)) and mask value register (806(1,1) to 806(1,4)) includes a lower data input (LD) coupled the output of a CAM cell in the lower row.

Ternary content addressable memory (CAM) having fast insertion and

An improved laser fusible link structure for semiconductor devices (200) and method of manufacturing thereof (10) is disclosed. A first conductive layer is patterned to create a laser fuse (202) and then covered with a first dielectric layer (212). An etch mask layer, in the preferred embodiment a second layer of polysilicon, is deposited and patterned to form a fuse etch mask (214) directly over the laser fuse (202). The fuse etch mask (214) has a width that is smaller than a minimum laser spot size, but large enough to protect the laser fuse (202) from fuse window over-etch, taking into account any potential misalignment between the laser fuse (202) and the fuse etch mask (214).

Fusible link structure for semiconductor devices

Laser fusible link structure for semiconductor devices

An output buffer circuit with low power pre-output driving capability uses existing output drivers and includes input inverters with three-state outputs interposed between the input and output stages and a feedback circuit with three-state outputs connected to the output stage. During normal data transmission, the input inverters buffer the incoming complementary data signals driving the pull-up and pull-down transistors in the output stage while the three-state outputs of the feedback circuit are turned off. Upon receiving an active pre-output control signal, the input inverters are disabled, thereby isolating the pull-up and pull-down transistors from the incoming complementary data signals, and the feedback circuit is enabled. The enabled feedback circuit monitors the signal level of the output signal from the output stage. When the output signal is a logic 0, the feedback circuit turns the pull-up and pull-down transistors on and off, respectively, and when the output signal is a logic 1, the feedback circuit turns the pull-up and pull-down transistors off and on, respectively. Once the output signal has reached the desired pre-output signal level intermediate to the normal logic 0 and logic 1 levels, the feedback circuit rams off both the pull-up and pull-down transistors. Accordingly, an output signal at the desired pre-output signal level is provided with no DC power consumption by the output stage.

Output buffer circuit with low power pre-output drive

A synchronous burst SRAM (110) is disclosed that includes a clock circuit (112) having a phase correction subcircuit (134) and a clock routing subcircuit (132). The clock routing subcircuit (132) provides an internal clock signal to at least one clocked circuit. The phase correction subcircuit (134) is a modified phase locked loop that includes a phase comparator (138) that receives an external clock signal and a delayed internal clock signal. In response to the signals, the phase comparator (138) provides a phase error signal to a charge pump (140) which is coupled to a loop filter (142) to provide an error voltage. The error voltage is coupled to a VCO (144) which provides the internal clock signal as an output. The internal clock signal is coupled to the input of the phase comparator (138) by a feedback circuit which generates the delayed internal clock signal for the phase comparator (138). The feedback circuit can include a number of delay elements (146) to simulate the clock delay inherent in the clock routing subcircuit (132) so that the resulting internal clock signal is phase shifted to compensate for delays caused by the clock routing subcircuit (132).

Phase shift correction circuit for monolithic random access memory

A timing delay modulation scheme for integrated circuits (10) is disclosed. A super voltage is applied to existing bond pads (30) and detected by super voltage detect circuits (34) which generate a number of logic input signals (22) to a logic unit (18). In response, the logic unit (18) provides a number of control signals (24) which are coupled to timing adjust circuits (20). In the preferred embodiment, in response to its respective control signals, each timing adjust circuit (20) pushes-out or pulls-in, a separate internal timing signal (S0-S3) of the integrated circuit. The super voltage detect circuit (34) includes an adjustable effective super voltage level, and is capable of being disabled. Further, the timing adjustment provided by each timing adjust circuit (20) can be altered.

Timing delay modulation scheme for integrated circuits

A burst mode static random access memory (SRAM) (10) is disclosed that includes an address transition detect signal (ATD) generating circuit (14) that provides either an asynchronous ATD signal (a-ATD) or a synchronous ATD signal (s-ATD) depending upon the logic state of a mode signal (ATM). A rising edge of the a-ATD signal is generated by a change in address. A falling edge is generated after a predetermined time period according an a-ATD circuit (60) within the ATD generating circuit (14). A falling edge of the s-ATD signal is generated by a rising edge of an internal synchronous clock pulse (CLAT). The rising edge of the s-ATD signal is generated when data are sensed on data lines (40) by an end-of-cycle circuit (20). If ATM is high, the a-ATD signal is used for timing on the SRAM (10). If ATM is low, timing is determined according to the s-ATD signal. An ATD control circuit (16) is provided to generate I/O control signals in response to the ATD signal (either s-ATD or a-ATD). On a rising edge of the ATD signal the I/O control signals place the SRAM (10) in a precharge/equalization state wherein I/O lines (24, 32, 40) are equalized and sensing circuits (28, 34) are disabled. On a falling edge of the ATD signal, the SRAM (10) is placed in a read/write mode wherein the I/O lines (24, 32, 40) are ready to sense read data or be driven by written data, and sensing circuits (28, 34) are enabled for a read operation, or alternatively disabled for a write operation.

Synchronous static random access memory having asynchronous test mode

An address transition detection (ATD) circuit provides an address transition detection pulse in response to either a high-to-low or low-to-high external address transition. The ATD circuit includes an address buffer that translates an externally applied address signal into an internal address signal and its logical complement. Two delay chains, each of which includes inverters, capacitors, a NAND gate and a CMOS pass gate, combine with the address buffer and an n-channel pull-down transistor to provide the ATD circuit. The outputs of the CMOS pass-gates are connected to the gate of the pull-down transistor. The drain of the pull-down transistor serves as the local ATD node of a dual-load feed-back controlled ATD pulse generator. The ATD local node is common to address buffers that select memory cells within a particular memory block. Address buffers responsible for switching between blocks have separate feedback-controlled ATD pulse generators in order to optimize the access time of the memory device.

High speed and hierarchical address transition detection circuit

A design approach for a tree structure multiplexer produces a compact circuit layout by reducing the required number of transistors. The multiplexer is used to perform a binary decode of the input signals to generate a single selection of one of a number of potential outputs. since the inputs undergo a binary decode, the number of outputs is equal to 2.sup.x, where x is the number of inputs.

Compact multiplexer circuit

Hierarchical redundancy is implemented in a monolithic memory by providing standard row and column redundancy augmented by redundant blocks, each having its own internal row and block redundancy. The efficiency of the redundant blocks is further enhanced by subdividing the redundant blocks into individually replaceable segments of rows or columns. A test and repair algorithm utilizing the hierarchical redundancy scheme is also provided.

Hierarchical redundancy scheme for high density monolithic memories

A memory array wherein transfer bus length is reduced and segmented by arranging the column decoder select signals to run across the length of the word line to reduce the node capacitance seen by the corresponding memory cell. This transfer of low capacitance from the transfer bus, i.e., the critical path, to the select line, which is a non-critical path for speed, improves access speed.

Segmented bus architecture for improving speed in integrated circuit

An address detection transition circuit provides an address transition detection pulse in response to either a high-to-low or a low-to-high external address input logic transition. The address transition detection circuit includes an address input buffer that responds to the external address input by providing first and second complimentary signals at first and second address input buffer output nodes, respectively. A first delay chain connected between the first address input buffer output node and the buffer output node responds to a high-to-low external address input logic transition by providing a logic high signal at the buffer output node. Similarly, a second delay chain connected between the second address input buffer output node and the buffer output node responds to a low-to-high external address input logic transition by providing a logic high signal at the buffer output node. A pull-down device responds to a logic high signal at the buffer output node by generating a logic low address transition detection pulse at the address transition detection node. A feedback controlled network connected to the address transition detection node controls the pulse width of the address transition detection pulse.

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San Jose, CA, United States of America

Ajit K Medhekar