International Business Machines Corporation

Ultratech, Inc.

Ajay Prabhakar Giri

Da-Yuan Shih

Roy Rongqing Yu

Eric D Perfecto

Tien-Jen Cheng

Joseph Michael Sullivan

Peter A Agostino

John Ulrich Knickerbocker

Paul Alfred Lauro

Lisa M Studzinski

Luc L Belanger

Voya Rista Markovich

Keith Kwong Hon Wong

Sampath Purushothaman

Christian Lavoie

Hilton T Toy

Jon Alfred Casey

Stephen L Buchwalter

David L Edwards

Sung Kwon Kang

Rajesh Bhikhubhai Patel

Charles Hampton Perry

Sarah Huffsmith Knickerbocker

Kamalesh K Srivastava

James N Humenik

Lewis Sigmund Goldmann

Chandrika Prasad

Lawrence D David

Srinivasa S Reddy

Donald W Henderson

Herbert I Stoller

Robert W Nufer

Giulio DiGiacomo

Leena Paivikki Buchwalter

Christopher Lee Tessler

Mark A Takacs

Jonathan H Griffith

Paul Robert Walling

Kimberley A Kelly

John Acocella

Steven M Kandetzke

Michael J Sullivan

Daniel P O'Connor

George Czornyj

Renuka S Divakaruni

Anton Nenadic

Ashwani K Malhotra

Bouwe W Leenstra

Richard A Bates

Anthony Mastreani

Eric H Laine

John R Pennacchia

Arnold I Baise

Lovell B Wiggins

Daniel P Kirby

David R Clarke

Salvatore J Scilla

Liang-Choo Hsia

Valérie Anne Oberson

Amy T Matts

Werner E Dunkel

Allen J Dam

Ray M Bryant

Todd M Fowler

Blessen Samuel

Richard L Canull

David Clifford Long

Marc Adam Bergendahl

Subhash Laxman Shinde

Rajesh S Patel

Rao Venkateswara Vallabhaneni

Carlton G Willson

Mukta S Farooq

Daniel Joseph Dawson

Hiroyuki Hiraoka

Valerie A Oberson

Sundar M Kamath

John R Lankard

Sundar Mangalore Kamath

Ron J McDonald

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers

Methods and UBM structures having bilayer or trilayer UBM layers that include a thin TiW adhesion layer and a thick Ni-based barrier layer thereover both deposited under sputtering operating conditions that provide the resultant bilayer or trilayer UBM layers with minimal composite stresses. The Ni-based barrier layer may be pure Ni or a Ni alloy. These UBM layers may be patterned to fabricate bilayer or trilayer UBM capture pads, followed by joining a lead-free solder thereto for providing lead-free solder joints that maintain reliability after multiple reflows. Optionally, the top layer of the trilayer UBM structures may include soluble or insoluble metals for doping the lead-free solder connections.

Structure of UBM and solder bumps and methods of fabrication

Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers

A method of forming a multichip module in which a thin film structure is formed on a temporary carrier and then an electrically insulating frame is attached to the thin film structure. A semiconductor device is attached to the thin film structure and then the temporary carrier is removed. Lastly, at least one semiconductor device is attached to the other side of the thin film structure. There is interconnectvity through the thin film structure between the semiconductor devices and the frame.

Method of forming a multichip module having chips on two sides

A process for electroplating metallic features of different density on a surface of a substrate comprises providing an electroplating bath having an anode, immersing the substrate into the electroplating bath, spaced from the anode, the substrate comprising a cathode. Positioned in the electroplating bath between the substrate and the anode, and adjacent to and separated from the substrate surface is a second cathode that includes a wire mesh screening portion having openings of different sizes conforming to the metallic features to be electroplated. The second cathode screening portion has openings of larger size adjacent areas of higher density of features to be electroplated and openings of smaller size adjacent areas of lower density of features to be electroplated. The process further includes impressing a current through the electroplating bath between the substrate and the anode, and between the second cathode and the anode, and electroplating the metallic features of different density onto the substrate.

Method for controlling local current to achieve uniform plating thickness

Method and apparatus for controlling local current to achieve uniform plating thickness

A multichip module including a frame having contacts suitable for making an electrical connection with an article, preferably a printed wiring board or similar, which is the next level of packaging, a multilayer thin film structure mounted to the frame, and semiconductor devices mounted to the thin film structure with at least one semiconductor device on each of two opposed sides of the thin film structure. The thin film structure includes arrays of pads on opposed surfaces of the thin film structure for connecting the thin film structure to the semiconductor devices and the frame. The thin film structure further includes wiring for chip to chip connectivity and for connecting to the frame.

Multichip module having chips on two sides

A structure for mounting electronic devices. The structure uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.

Process for forming a multi-level thin-film electronic packaging structure

A heat sink assembly and method for attaching a multi-chip module cap to a polymeric heat sink adhesive by means of a thin adhesion-promoting metal film layer, which provides an interfacial bond between the cap and polymeric adhesive meeting package performance and reliability requirements. There is also a method of promoting adhesion between a silicon-containing polymeric adhesive and a metal surface using the thin adhesion-promoting metal film layer and the products thereof.

Method using a thin adhesion promoting layer for bonding silicone elastomeric material to nickel and use thereof in making a heat sink assembly

A process for fabricating a microelectronic structure. The process comprises processing a metal carrier having a top surface and a bottom surface, wherein the top surface and the bottom surface are processed to promote adhesion, forming a dielectric layer around the metal carrier, wherein the dielectric layer substantially covers the top surface and the bottom surface of the metal carrier, and applying a first patterned layer of conductive material to the microelectronic structure. In one preferred embodiment, the process further comprises comprising sintering the metal carrier, the dielectric layer, and the first patterned layer of conductive material. In one preferred embodiment, the process further comprises forming a via hole through the metal carrier before the forming of the dielectric layer around the metal carrier, wherein the forming of the dielectric layer comprises forming the dielectric layer inside the via hole.

Structure and process for making substrate packages for high frequency application

A structure for mounting electronic devices which uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.

Multi-level thin-film electronic packaging structure and related method

A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer. At least one mounting location suitable for mounting an electronic component is formed on the second dielectric layer. The substrate may be attached a printed circuit board by direct attachment, pin grid array (PGA), land grid array (LGA), ball grid array (BGA), column grid array (CGA) and miniBGA on the bottom layer of the ceramic base.

Direct deposit thin film single/multi chip module

A process for producing a terminal metal pad structure electrically interconnecting a package and other components. More particularly, the invention encompasses a process for producing a plurality of corrosion-resistant terminal metal pads. Each pad includes a base pad containing copper which is encapsulated within a series of successively electroplated metal encapsulating films to produce a corrosion-resistant terminal metal pad.

Corrosion-resistant terminal metal pads for thin film packages

Process for producing corrosion-resistant terminal metal pads for thin

A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer. At least one mounting location suitable for mounting an electronic component is formed on the second dielectric layer. The substrate may be attached a printed circuit board by direct attachment, pin grid array (PGA), land grid array (LGA), ball arid array (BGA), column grid array (CGA) and miniBGA on the bottom layer of the ceramic base.

Growing community of inventors

Poughkeepsie, NY, United States of America

Ajay Prabhakar Giri