Motorola Corporation

Ajay Jain

Robert E Jones

Peter Zurcher

Elizabeth J Weitzman

Peir-Yung Chu

Olubunmi O Adetutu

Robert W Fiordalice

Kevin D Lucas

Matthew Thomas Herrick

Dean J Denning

Cindy Reidsema Simpson

Ramnath Venkatraman

Cristiano Capasso

Robert L Hance

Gregor Braeckelmann

Rina Chowdhury

A refractory Metal Nitride and a refractory metal Silicon Nitride layer ( ) can be formed using metal organic chemical deposition. More specifically, tantalum nitride (TaN) ( ) can be formed by a Chemical Vapor Deposition (CVD) using Ethyltrikis (Diethylamido) Tantalum (ETDET) and ammonia (NH ). By the inclusion of silane (SiH ), tantalum silicon nitride (TaSiN) ( ) layer can also be formed. Both of these layers can be formed at wafer temperatures lower than approximately 400&deg; C. with relatively small amounts of carbon (C) within the film. Therefore, the embodiments of the present invention can be used to form tantalum nitride (TaN) or tantalum silicon nitride (TaSiN) ( ) that is relatively conformal and has reasonably good diffusion barrier properties.

Method of forming a semiconductor device

A method for forming a copper interconnect begins by depositing a barrier layer (,) within an in-laid region (,). An edge exclusion protection layer (,) is formed over the barrier layer (,), and this layer (,) is processed so that it only lies within the edge exclusion region (,) of the wafer. The layer (,) is removed from active area portions of the wafer so that contact resistance of copper interconnects is not affected. Wet surface processing is used to form a catalyst (,) on the wafer surface to enable electroless copper plating within active areas of the wafer to form a copper seed layer (,). The layer (,) is not formed in an edge exclusion region (,). Electroplating is then used to thicken the copper material to form a copper layer (,) over the layer (,) wherein the in-laid copper interconnect is completed.

Method for protecting the edge exclusion of a semiconductor wafer from copper plating through use of an edge exclusion masking layer

An interconnect (,) is formed overlying a substrate (,). In one embodiment, an adhesion/barrier layer (,), a copper-alloy seed layer (,), and a copper film (,) are deposited overlying the substrate (,), and the substrate (,) is annealed. In an alternate embodiment, a copper film is deposited over the substrate, and the copper film is annealed. In yet another embodiment, an adhesion/barrier layer (,), a seed layer (,), a conductive film (,), and a copper-alloy capping film (,) are deposited over the substrate (,) to form an interconnect (,). The deposition and annealing steps can be performed on a common processing platform.

Method for forming a semiconductor device

A refractory Metal Nitride and a refractory metal Silicon Nitride layer (64) can be formed using metal organic chemical deposition. More specifically, tantalum nitride (TaN) (64) can be formed by a Chemical Vapor Deposition (CVD) using Ethyltrikis (Diethylamido) Tantalum (ETDET) and ammonia (NH.sub.3). By the inclusion of silane (SiH.sub.4), tantalum silicon nitride (TaSiN) (64) layer can also be formed. Both of these layers can be formed at wafer temperatures lower than approximately 400.degree. C. with relatively small amounts of carbon (C) within the film. Therefore, the embodiments of the present invention can be used to form tantalum nitride (TaN) or tantalum silicon nitride (TaSiN) (64) that is relatively conformal and has reasonably good diffusion barrier properties.

Method of forming a barrier layer

A method for forming CMOS transistors and ferroelectric capacitors on a single substrate (10) with improved yield begins by forming CMOS transistors (37a, 37b, 40, 42). A hydrogen anneal using 4-5% hydrogen and a remainder nitrogen is performed to reduce dangling atomic bonds at the gate dielectric/substrate interface of the transistors (37a, 37b, 40, 42). A silicon nitride layer (48) is then deposited over the transistors and on the backside of the wafer substrate (10) in order to substantially encapsulate the effects of the hydrogen anneal to the CMOS transistors (37a, 37b, 40, 42). Ferroelectric capacitor layers (54, 58, 60, 62, 64) are formed overlying the nitride layer (48) where the ferroelectric capacitor layers (54, 58, 60, 62, 64) are oxygen annealed in pure O.sub.2. The nitride layer (48) prevents the transistor hydrogen anneal from damaging the ferroelectric material by containing the hydrogen.

Method for making a ferroelectric device having a tantalum nitride

A method for forming a copper interconnect (54) begins by depositing a barrier layer (48). An intermediate layer (50) is formed over the barrier layer (48) by exposing the barrier layer (48) to a plasma silane environment. The layer (50) is conductive when deposited so that contact resistance is not affected. The layer (50) is insitu covered with a copper seed layer (52). The layer (52) is not formed in an edge exclusion region (20) thereby exposing a portion (50a) of the layer (50). This portion (50a) will natively oxidize in a room ambient to form a copper electroplating prevention barrier whereby copper will not electroplate in the region (20). Therefore, the region (50a) prevents barrier-to-copper interfaces to avoid delamination of the copper while preserving the edge exclusion region desired for copper electroplating.

Method for preventing electroplating of copper on an exposed surface at

A method and apparatus for detecting copper (Cu) contamination on the backside of a wafer (120) begins by providing the wafer (120). The wafer (120) is rotated about a rotational axis via a motor/computer controlled wafer stage (118). In addition to rotation of the wafer (120), motor/computer control of a monochromator (116) is used to raster scan an X-ray beam (114b) across a surface of the rotating wafer (120). A plurality of X-ray detectors (122) are arrayed in one or more rows in close proximity to the scanned surface of the semiconductor wafer (120). The detectors (122), detect X-ray fluorescence emission from the surface of the wafer (120) whereby copper contamination of the wafer (120) can be determined in an accurate and time efficient manner which enables contamination detection in-line with normal wafer processing.

Method and apparatus for in-line measuring backside wafer-level

A process for forming a semiconductor device (68) in which an insulating layer (52) is nitrided and then covered by a thin adhesion layer (58) before depositing a composite copper layer (62). This process does not require a separate diffusion barrier as a portion of the insulating layer (52) has been converted to form a diffusion barrier film (56). Additionally, the adhesion layer (58) is formed such that it can react with the interconnect material resulting in strong adhesion between the composite copper layer (62) and the diffusion barrier film (56) as well as allow a more continuous interconnect and via structure that is more resistant to electromigration.

Process for forming a semiconductor device

The present invention provides an anti-reflective Ta.sub.3 N.sub.5 coating which can be used in a dual damascene structure and for I line or G line lithographies. In addition, the Ta.sub.3 N.sub.5 coating may also be used as an etch stop and a barrier layer. A dual damascene structure is formed by depositing a first dielectric layer (16). A dielectric tantalum nitride layer (18) is deposited on top of the first dielectric layer. A second dielectric layer (20) is deposited on the tantalum nitride layer. A dual damascene opening (34) is etched into the dielectric layers by patterning a first opening portion (26) and a second opening portion (32) using photolithography operations. Dielectric tantalum nitride layer (18) serves as an ARC layer during these operations to reduce the amount of reflectance from conductive region (14) to reduce distortion of the photoresist pattern. The use of a dielectric tantalum nitride layer as an ARC is particularly suitable for I line and G line lithography.

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Austin, TX, United States of America

Ajay Jain