Globalfoundries Inc.

Ahmed Nayaz Noemaun

Geng Wang

Chengwen Pei

Shreesh Narasimha

Paul Christian Parries

Karen A Nummy

Katsunori Onishi

Bidan Zhang

Ravi K Dasaka

A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

Asymmetric stressor DRAM

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Beacon, NY, United States of America

Ahmed Nayaz Noemaun