Texas Instruments Corporation

Other

Agerico L Esquivel

Allan T Mitchell

Howard L Tigelaar

Robert Groover, Iii

A programmable memory device having slot trenches (,). A plurality of floating gates (,) are separated from a surface of semiconductor body (,) by a gate dielectric (,). A plurality of slot trenches (,) isolate memory cells (,) from each other. Each of the slot trenches (,) extends below the surface of the semiconductor body (,) between adjacent floating gates (,). A control gate (,) extends over the floating gates (,) and a portion of each of the slot trenches (,).

Slot trench isolation for flash EPROM

A nonvolatile memory array has two or more stacked layers of memory cells (10). The bottom layer may comprise a planar, X-cell, or buried N++ FAMOS transistor array and the top layer preferably comprises a planar transistor array. An epitaxial silicon layer (36) provides the substrate for the second layer. The stacked layer structure allows a two-fold increase in memory density without scaling the device sizes.

Method of forming a nonvolatile stacked memory

Bitlines (34) are formed by creating a diffused region (26) around the sidewalls and bottom of a trench (20). The trench (20) is filled with a conductive region (30), typically a refractory metal, refractory metal silicide.

Method of making an array device with buried interconnects

One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.

Floating gate memory cell and device

One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit lines resistivity for a given cell density.

Method of making a pleated floating gate trench EPROM

A non-volatile cross-point memory cell array comprises a trench isolated cross-point array of memory cells (10), which are electrically programmable and electrically FLASH eraseable, having diffused regions (28) operable as bitlines, each diffused region (28) traversed by a plurality of control gates (54) operable as wordlines. The diffused regions (28) undergo a silicidation process to decrease their resistivity, and thereby increase the speed of the memory cell array. A tunnel oxide (18) is provided for electrical erasing and programming. Planarized, high quality insulating regions (40, 36), such as dichlorosilane oxide, buttress the floating gate (20) to isolate the bitlines from the wordlines and to improve isolation between the pass gate and the floating gate. A planar structure of the memory cell (10) provides flat topography ideal for three dimensional stacked structures. Trench isolation regions (56) reduce bitline capacitance, thereby increasing programming speed.

Method of making fast, trench isolated, planar flash EEPROMS with

A cross point EPROM array has trenches to provide improved isolation between adjacent buried N+ bitlines at locations where the adjacent buried N+ bitlines are not separated by a FAMOS transistor. This results in improved leakage current, improved punchthrough voltage characteristics, and in improved programmability for the cell.

Non-volatile memory

A method and apparatus for providing interconnections between levels on a semiconductor substrate of various types includes first forming a plurality of trenches in the substrate and then forming conductive layers at the bottom of the trenches. The trenches are then filled with an oxide to provide a planar surface on the substrate. Various levels of trenches are provided with crossovers being formed by a bridging layer of a conductive material that is formed over an oxide layer in the lower level trenches. Vertical contacts are formed by etching an opening from the surface to the bottom of the trenches through the oxide layer and filling the opening with a metal plug.

Buried multilevel interconnect system

A non-volatie cross-point memory cell array comprises a trench isolated cross-point array of memory cells (10), which are electrically programmable and electrically FLASH eraseable, having diffused regions (28) operable as bitlines, each diffused region (28) traversed by a plurality of control gates (54) operable as wordlines. The diffused regions (28) undergo a silicidation process to decrease their resistivity, and thereby increase the speed of the memory cell array. A tunnel oxide (18) is provided for electrical erasing and programming. Planarized, high quality insulating regions (40, 36), such as dichlorosilane oxide, buttress the floating gate (20) to isolate the bitlines form the wordlines and to improve isolation between the pass gate and the floating gate. A planar structure of the memory cell (10) provides flat topography ideal for three dimensional stacked structures. Trench isolation regions (56) reduce bitline capacitance, thereby increasing programming speed.

Fast, trench isolated, planar flash EEPROMS with silicided bitlines

A sealed gate FAMOS transistor (28) disposes a thermal oxide layer (40) about the floating gate (34) in order to isolate the floating gate (34) from the planar isolating regions (44) between floating gates (34). Trench isolating regions (54) are provided between control gates (50) to enhance programmability of the sealed gate FAMOS transistor (28).

Planar famos transistor with trench isolation

Disclosed is a floating gate memory array having high-speed programming capabilities. Diffused buried bit lines (14) are formed spaced apart in a semiconductor, forming conduction channels therebetween. Dielectric-filled trenches (24) are formed between the bit lines (14). An insulated floating gate conductor (18) and an insulated control gate conductor (23) are formed over the wafer and patterned to extend over the dielectric-filled trenches (24). The enhanced coupling efficiency between the control gate (23) and the floating gate (18) enhances the programmability of the memory cells.

EPROM with increased floating gate/control gate coupling

The invention provides an EPROM having a high quality dielectric to separate the floating gate from low quality dielectric layers used in the prior art by the method outlined as follows. First, the polycrystalline silicon floating gates are formed and partially patterned on the surface of a substrate. A thin thermally grown oxide layer is then formed over the entire array. The source/drain regions are then implanted through the thin silicon dioxide layer into the substrate. Next a thick silicon dioxide layer is deposited by chemical vapor deposition on the surface of the array. The surface of the array is then coated with photoresist which, because of its nature, provides a planarized surface on the top layer of photoresist. The photoresist and the silicon dioxide layer are then etched using an etching process which provides an etching ratio of 1:1 between photoresist and silicon dioxide. The photoresist is completely etched away thus leaving the planarized silicon dioxide surface. The silicon dioxide layer is then further etched so that the top surfaces of the floating gates are exposed. An interlevel insulator layer is then formed on the surface of the array and the active gates are then formed on the surface of the interlevel insulator.

Growing community of inventors

Dallas, TX, United States of America

Agerico L Esquivel