Siemens Aktiengesellschaft

Adolf Scheibe

Ulrich Schwabe

Erwin P Jacobs

Burkhard Giebel

A method of producing a large-scale integrated MOS field effect transistor circuit which includes forming p and n-doped troughs, respectively, in a silicon substrate to accommodate respective n and p-channel transistors, introducing appropriate dopant atoms into the troughs by repeated ion implantations to adjust various transistor cutoff voltages, and masking the various ion implantations with photo resist structures and/or with silicon oxide and silicon nitride structures, respectively, and which includes forming source/drain and gate areas as well as forming intermediate and insulation oxide and a strip conductor plane in accordance with conventional MOS technology methods includes the steps of: applying a total-area oxide film having a first film thickness (d1.sub.G); removing the oxide in a given area (II) associated with an n-channel transistor; and applying another, total-area oxide film in such a manner that, in anothedr area (III) associated with another n-channel transistor, the oxide film attains a final thickness (d.sub.G) which is greater than the first film thickness (d1.sub.G), may be followed by the steps of: applying a mask to a gate oxide with a window in a given area (II); implanting with first dopant atoms to produce n.sup.+ source/drain areas of a first n-channel transistor, dosage and implantation energy thereof being adapted to a second film thickness (d3.sub.G) of the gate oxide; applying a mask to a gate oxide with a window in another area (III); implanting with second dopant atoms to produce an n+ source/drain area of a second n-channel transistor, the dosage and implantation energy thereof being adapted to a final thickness (d.sub.G); removing that part of the gate oxide surface which is contaminated; and driving the implanted dopant atoms into the given area (II) and the other area (III).

Method of producing a large-scale integrated MOS field-effect transistor

Complementary MOS field effect transistor circuits are produced in silicon gate technology, with the method steps up to the structuring of the gate electrode being executed in a known manner. Both source/drain implantations (FIG. 3, 8 and FIG. 5, 10) occur with only one mask (7a). This mask (7a), which is composed of silicon nitride, is utilized for the source/drain implantation 8 of the n-channel transistors (9). The source/drain implantation (10) for the p-channel transistors (11) occurs without a mask and the oxide layer thickness, d.sub.6, over the source/drain regions of the n-channel transistors (9) functions as a masking layer. An advantage of this process sequence is that switched capacitor structures (FIG. 6, 5b, 12) can be simultaneously produced whereby the oxide layer thickness, d.sub.4, over the polysilicon-1 level (5a, 5b) determines the thickness of the insulating layer, d.sub.cox, of the capacitor structures (5b, 12). This technique is useful for manufacturing VLSI CMOS circuits in VLSI technology with and without switched capacitors.

Method for manufacturing VLSI complementary MOS field effect transistor

Reprogrammable semiconductor read-only memory with memory cells of the floating-gate type, including an additional potential carrier for each memory cell for capacitively coupling a further potential to the floating gate.

Reprogrammable semiconductor read-only memory of the floating-gate type

A method of producing a monolithically integrated two-transistor memory cell, including a silicon crystal for accommodating the memory cell, a first MOS field effect transistor having a current-carrying channel and both a control gate and a floating gate disposed between the control gate and surface of the crystal, a second MOS field effect transistor having a current-carrying channel and a control gate, an SiO.sub.2 film supporting the gates, a doped polycrystalline silicon layer deposited on the SiO.sub.2 film, the control gates and the floating gate being formed from the doped polycrystalline silicon layer, and an erase area for the floating gate, the improvement which includes covering a part of the silicon crystal intended for the memory cell with an SiO.sub.2 film, forming a part of the gate oxide of the first MOS field effect transistor, forming a window through the SiO.sub.2 film at a location intended for the erase area, re-oxidizing the exposed area of the surface of the crystal in the window and increasing the remaining areas of the SiO.sub.2 film, depositing a first doped polycrystalline silicon layer forming a base of the floating gate, covering the polycrystalline silicon layer with another SiO.sub.2 film, depositing a second doped polycrystalline silicon layer, and forming the control gate of the first MOS field effect transistor from the second doped polycrystalline silicon layer and producing the source and drain zone of the two MOS field effect transistors.

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Ottobrunn, Germany

Adolf Scheibe