Intel Corporation

Adhiveeraraghavan Srikanth

Luke A Johnson

Wenjun Yun

Navneet Dour

Sanjib Sarkar

Yun He

Subrata Mandal

In accordance with embodiments disclosed herein, there is provided systems and methods for jitter sensing and adaptive control of parameters of clock and data recovery (CDR) circuits. A receiver component includes an adaptive CDR loop dynamic control circuit. The adaptive CDR loop dynamic control circuit is to detect first sinusoidal jitter at a first frequency and a first amplitude and update parameters of the CDR circuit to a first plurality of values based on the first frequency and the first amplitude. The adaptive CDR loop dynamic control circuit is further to detect second sinusoidal jitter at a second frequency and a second amplitude and update the parameters of the CDR circuit to a second plurality of values based on the second frequency and the second amplitude. The first sinusoidal jitter is in a first incoming data signal and the second sinusoidal jitter is in a second incoming data signal.

Jitter sensing and adaptive control of parameters of clock and data recovery circuits

Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

Method and apparatus for minimizing within-die variations in performance parameters of a processor

In one embodiment, a pre-driver generates pre-driving signals based on control signals provided by a control circuit. The pre-driver has pre-driver power and ground connections. The pre-driving signals operate at a frequency band. A driver generates an output signal based on the pre-driving signals at an output pad. The output signal has a slew rate. The driver has driver power and ground connections. A low pass filter is coupled between the pre-driver and the driver power and ground connections to reduce the effect of noise at the pre-driving signals. The low pass filter has a cut-off frequency corresponding to the frequency of noise. In another embodiment, a plurality of pre-drivers generates pre-driving signals based on control signals provided by a control circuit. The pre-drivers have pre-driver power and ground connections. A plurality of drivers generates a plurality of output signals based on the pre-driving signals at output pads of an integrated circuit. Each of the output signals has a slew rate. The drivers have driver power and ground connections. On-die pre-driver power and ground planes are coupled to the pre-driver power and ground connections on die of the integrated circuit, respectively. On-die driver power and ground planes are coupled to the driver power and ground connections on-die of the integrated circuit, respectively. The driver power and ground planes are separated from the pre-driver power and ground planes on the die, and/or on the package to maintain the desired slew rate.

Slew rate at buffers by isolating predriver from driver

A valid data strobe detection technique detects a valid data strobe contained within a strobe signal by first determining whether a measured voltage level of the strobe signal is above or below a preselected threshold level. A time period in which the measured voltage level is continuously one of either above or below the preselected threshold level is then measured and a valid data strobe is detected upon the measured time period being greater than a preselected period of time. A comparator may be used to determine whether the measured voltage level of the strobe signal is above or below the preselected threshold level and a sample and hold unit may be used to measure the time period in which the strobe signal is one of either above or below the preselected threshold level.

Valid data strobe detection technique

A differential amplifier power supply is derived from the same source that generates the reference voltage for the differential amplifiers. This will ensure the direction of voltage level shifts of these two voltages to be in tandem. That is, these two voltages will move in the same direction due to any variations in the source since they are generated from the same regulator. In this way receiver timing errors can be significantly reduced in source synchronous and common clock interfaces.

AC timings at the input buffer of source synchronous and common clock designs by making the supply for differential amplifier track the reference voltage

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Folsom, CA, United States of America

Adhiveeraraghavan Srikanth