Sandisk Technologies Inc.

Adarsh Rajashekhar

Raghuveer S Makala

Fei Zhou

Rahul Sharangpani

Seung-Yeul Yang

Senaka Kanakamedala

Yanli Zhang

Joyeeta Nag

Kartik Sondhi

Roshan Jayakhar Tirukkonda

Bhagwati Prasad

Fumitaka Amano

Christopher John Petti

Tatsuya Hinoue

Akio Nishida

Ramy Nashed Bassely Said

Srikanth Ranganathan

Monica Titus

Genta Mizuno

Yusuke Mukae

Tomoyuki Obu

Tomohiro Uno

Toshihiro Iizuka

Masaaki Higashitani

Peter Rabkin

Masanori Tsutsumi

Koichi Matsuno

Lin Hou

Tiffany Santos

Bing Zhou

A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a first etch mask material layer, forming a first cladding liner, and forming a via opening through the alternating stack by performing an anisotropic etch process that employs a combination of at least the first cladding liner and the first etch mask material layer as a composite etch mask structure.

Method of making a three-dimensional memory device using composite hard masks for formation of deep via openings

A memory device includes a first electrically conductive line laterally extending along a first horizontal direction, a memory pillar structure overlying and contacting the first electrically conductive line, the memory pillar structure includes a vertical stack of a ferroelectric material plate and a selector material plate, and a second electrically conductive line laterally extending along a second horizontal direction and overlying and contacting the memory pillar structure.

Bonded memory devices and methods of making the same

A semiconductor memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of discrete ferroelectric material portions and a vertical semiconductor channel. In one embodiment, the discrete ferroelectric material portions include a ferroelectric alloy material of a first dielectric metal oxide material and a second dielectric metal oxide material. In another embodiment, each of the discrete ferroelectric material portions is oxygen-deficient.

Memory device containing composition-controlled ferroelectric memory elements and method of making the same

A semiconductor structure includes a doped single crystalline semiconductor material layer, a metal or metal alloy source contact layer located over a back side of the doped single crystalline semiconductor material layer, a dielectric isolation layer located over a front side of the doped single crystalline semiconductor material layer, an alternating stack of insulating layers and electrically conductive layers located over the dielectric isolation layer, a memory opening vertically extending through the alternating stack and the dielectric isolation layer and at least partially through the doped single crystalline semiconductor material layer, a memory film and a vertical semiconductor channel located within the memory opening, such that the vertical semiconductor channel vertically extends through the dielectric isolation layer and into the doped single crystalline semiconductor material layer, and a single crystalline semiconductor pedestal contacting the doped single crystalline semiconductor material layer and the vertical semiconductor channel.

Three-dimensional memory device containing epitaxial pedestals and top source contact

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical stack of charge storage elements, a vertical semiconductor channel, a ferroelectric material layer located between the vertical stack of charge storage elements and the vertical semiconductor channel, and a blocking dielectric layer located between the ferroelectric material layer and the vertical semiconductor channel. A tunneling dielectric layer is located between at least one of the electrically conductive layers and the vertical stack of charge storage elements.

Three-dimensional memory device containing ferroelectric-assisted memory elements and method of making the same

A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening extending vertically through the alternating stack and including laterally-protruding portions at levels of the electrically conductive layers, and a memory opening fill structure located in the memory opening and containing a vertical semiconductor channel and a vertical stack of discrete ferroelectric memory structures located in the laterally-protruding portions of the memory opening. Each of the ferroelectric memory structures includes crystalline ferroelectric material portion and a crystalline template material portion located between a respective electrically conductive layer of the electrically conductive layers and the crystalline ferroelectric material portion.

Three-dimensional memory device containing templated crystalline ferroelectric memory elements and method of making thereof

A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a mask layer over the alternating stack, forming a cavity in the mask layer, forming a first cladding liner on a sidewall of the cavity in the mask layer, and forming a via opening the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavity in the mask layer through the alternating stack using a combination of the first cladding liner and the mask layer as an etch mask.

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.

Three-dimensional memory device including vertical stack of tubular graded silicon oxynitride portions

A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

Ferroelectric devices including a single crystalline ferroelectric layer and method of making the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.

Three-dimensional memory device with vertical word line barrier and methods for forming the same

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, etch stop plates located in the staircase region, laterally and vertically spaced apart among one another, and overlying an end portion of a respective one of the electrically conductive layers, and contact via structures located in a staircase region, vertically extending through a respective one of the etch stop plates, and contacting a respective one of the electrically conductive layers.

Three-dimensional memory device with word-line etch stop liners and method of making thereof

A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

Semiconductor device containing bit lines separated by air gaps and methods for forming the same

A three-dimensional memory device includes an alternating stack of source layers and drain layers located over a substrate, a memory opening vertically extending through the alternating stack, a vertical word line located in the memory opening and vertically extending through each of the source layers and the drain layers of the alternating stack, discrete semiconductor channels contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers, and a vertical stack of discrete memory material portions laterally surrounding the vertical word line.

Three-dimensional NOR array including vertical word lines and discrete memory elements and methods of manufacture

A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

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Santa Clara, CA, United States of America

Adarsh Rajashekhar