Applied Materials, Inc.

Varian Semiconductor Equipment Associates, Inc.

Maxim Integrated Products, Inc.

University of California

Adam Brand

John J Hautala

Simon Ruffell

Marco A Zuniga

Huixiong Dai

Naomi Yoshida

Badredin Fatemizadeh

Rajwinder Singh

Chi-Nung Ni

Tom K Castro

Bingxi Sun Wood

John Xia

Yihwan Kim

Steven Robert Sherman

Ludovic Godet

Srinivas D Nemani

Mei Yin Chang

David P Thompson

Christopher Dennis Bencher

Seshadri Ganguli

Shahid Rauf

Leonid Dorf

Benjamin Colombeau

Yi-Chiau Huang

Andrew C Kummel

Vijay Parihar

Shiyu Sun

Errol C Sanchez

Shariq Siddiqui

Dapeng Wang

Naushad K Variam

Lin Dong

Mandar Balasaheb Pandit

Subhash Deshmukh

Bhushan N Zope

Mathew Abraham

Renhe Jia

Aneesh Nainani

Tzay-Fa Su

Yuri Erokhin

Bhagawan Sahu

John Boland

Kasra Sardashti

Tobin Kaufman-Osborn

Nilay A Pradhan

Liming Zhang

Tyler Kent

Min Xu

A method of patterning a substrate. The method may include providing a surface feature on the substrate, the surface feature having a first dimension along a first direction within a substrate plane, and a second dimension along a second direction within the substrate plane, wherein the second direction is perpendicular to the first direction; and directing first ions in a first exposure to the surface feature along the first direction at a non-zero angle of incidence with respect to a perpendicular to the substrate plane, in a presence of a reactive ambient containing a reactive species; wherein the first exposure etches the surface feature along the first direction, wherein after the directing, the surface feature retains the second dimension along the second direction, and wherein the surface feature has a third dimension along the first direction different than the first dimension.

Techniques to engineer nanoscale patterned features using ions

A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.

LDMOS transistors including vertical gates with multiple dielectric sections, and associated methods

A method of treating a substrate includes directing ions to the substrate along at least one non-zero angle with respect to a perpendicular to a substrate surface in a presence of a reactive ambient containing a reactive species where the substrate includes a surface feature. At least one surface of the surface feature is etched using the ions in combination with the reactive ambient at a first etch rate that is greater than a second etch rate when the ions are directed to the substrate without the reactive ambient and greater than a third etch rate when the reactive ambient is provided to the substrate without the ions.

Techniques for processing substrates using directional reactive ion etching

A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.

Transistors with dual gate conductors, and associated methods

A dual-gate, self-aligned lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure, a lateral gate including a first dielectric layer and a first conductive layer stacked on the silicon semiconductor structure in a thickness direction, and a vertical gate. The vertical gate includes a second dielectric layer and a second conductive layer disposed in a trench of the silicon semiconductor structure, the second dielectric layer defining an edge of the lateral gate in a lateral direction. A method for forming a dual-gate, self-aligned LDMOS transistor includes (a) forming a vertical gate of the LDMOS transistor in a trench of a silicon semiconductor structure and (b) defining a lateral edge of a lateral gate of the LDMOS transistor using the vertical gate.

Self-aligned, dual-gate LDMOS transistors and associated methods

Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S&#x2014;H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200&#xb0; C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III-V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200&#xb0; C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.

Low temperature atomic layer deposition of oxides on compound semiconductors

Methods for forming a multi-threshold voltage device on a substrate are provided herein. In some embodiments, the method of forming a multi-threshold voltage device may include (a) providing a substrate having a first layer disposed thereon, wherein the substrate comprises a first feature and a second feature disposed within the first layer; (b) depositing a blocking layer atop the substrate; (c) selectively removing a portion of the blocking layer from atop the substrate to expose the first feature; (d) selectively depositing a first work function layer atop the first feature; (e) removing a remainder of the blocking layer to expose the second feature; and (f) depositing a second work function layer atop the first work function layer and the second feature.

Multi-threshold voltage (Vt) workfunction metal by selective atomic layer deposition (ALD)

A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs; forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure; subsequently forming a source region adjacent a first end of the superlattice structure and a drain region adjacent a second opposing end of the superlattice structure; and selectively etching the superlattice structure to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure.

Methods and apparatus for forming horizontal gate all around device structures

An electron beam plasma source is used in a soft plasma surface treatment of semiconductor surfaces containing Ge or group III-V compound semiconductor materials.

Interface treatment of semiconductor surfaces with high density low energy plasma

A method to selectively process a three dimensional device, comprising providing a substrate having a first surface that extends horizontally, the substrate comprising a structure containing a second surface that extends vertically from the first surface; providing a film on the substrate, the film comprising carbon species; and etching a selected portion of the film by exposing the selected portion of the film to an etchant containing hydrogen species, where the etchant excludes oxygen species and fluorine species.

Technique for selectively processing three dimensional device

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Palo Alto, CA, United States of America

Adam Brand