Intel Corporation

Other

Intel Corporatiion

Abhishek A Sharma

Van H Le

Jack T Kavalieros

Gilbert W Dewey

Tahir Ghani

Ravi Pillarisetty

Prashant Majhi

Brian S Doyle

Willy Rachmady

Shriram Shivaraman

Wilfred Gomes

Elijah V Karpov

Benjamin Chu-Kung

Ram K Krishnamurthy

Bernhard Sell

Gregory Kengho Chen

Phil Knag

Huseyin Ekin Sumbul

Travis W LaJoie

Sasikanth Manipatruni

Ian A Young

Seung Hoon Sung

Raghavan Kumar

Amrita Mathuriya

Yih Wang

Pei-Hua Wang

Mauro J Kobrinsky

Sean T Ma

Hui Jae Yoo

Chieh-Jen Ku

Matthew V Metz

Urusa Alaan

Nazila Haratipour

Aaron D Lilak

Arnab Sen Gupta

Christopher J Jezewski

Justin R Weber

Kevin Lai Lin

Ashish Agrawal

Carl H Naylor

Allen B Gardiner

Fatih Hamzaoglu

Shem Ogadhoh

Noriyuki Sato

Cheng-Ying Huang

Miriam Ruth Reshotko

Tristan A Tronic

Patrick R Morrow

Charles C Kuo

Elliot Tan

Doug B Ingerly

Rishabh Mehandru

Victor W Lee

Rafael Rios

Kaan Oguz

Manish Chandhok

Scott Bruce Clendenning

Roman Caudillo

Uygar E Avci

Sanaz Kabehie Gardner

Ehren Mannebach

Anand S Murthy

Kevin O'Brien

Harold W Kennel

Kimin Jun

Swaminathan Sivakumar

Cory E Weber

Anh Phan

Rajesh Kumar

Kevin Fischer

Pushkar Ranade

Marko Radosavljevic

Debendra Mallik

Omkar G Karhade

Ravindranath Vithal Mahajan

Nitin A Deshpande

Rami Hourani

Russell Y Webb

Kinyip Phoa

Lawrence D Wong

Jerremy Holland

Tomas Jon Pfister

Han Wui Then

Sansaptak W Dasgupta

Telesphor Kamgaing

James S Clarke

Jeanette M Roberts

Nicole K Thomas

Hubert C George

Sanka Ganesan

David L Kencke

Zachary R Yoscovits

Ilya V Karpov

Eungnak Han

Kanwaljit Singh

Nafees Kabir

Anup Pancholi

Gurpreet Singh

Huichu Liu

Ayan Kar

Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an 'angled transistor' if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. A component is referred to as a “backside component” if it is provided on the side of a semiconductor substrate that is opposite to the side over which the transistors of the memory arrays are provided. Memory arrays with backside components and angled transistors provide a promising way to increasing densities of memory cells on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

Memory arrays with backside components and angled transistors

Top-gate thin film transistor (TFTs) structures. Thin film transistors when in the top-gate configuration suffer from contact resistance. An example TFT includes a semiconductor layer doped with one or more dopant elements. A gate dielectric layer is on the semiconductor layer, and a gate electrode is on the gate dielectric layer. The semiconductor layer is doped with the one or more dopant elements beneath the gate dielectric layer. The TFT may further include one or more contacts and/or one or more gate spacers, and the semiconductor layer may further be doped with the one or more dopant elements beneath the contact(s) and/or gate spacer(s).

Top-gate doped thin film transistor

Embodiments of an integrated circuit (IC) die comprise a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; a second region comprising a semiconductor material, the second region attached to the first region along a first planar interface that is orthogonal to the first surface and parallel to the second surface; and a third region comprising optical structures of a photonic IC, the third region attached to the second region along a second planar interface that is parallel to the first planar interface. The first region comprises: a plurality of layers of conductive traces in a dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; and bond-pads on the first surface, the bond-pads comprising portions of respective conductive traces exposed on the first surface.

Package architecture of photonic system with vertically stacked dies having planarized edges

Embodiments of a microelectronic assembly comprise: a plurality of microelectronic sub-assemblies arranged in a coplanar array, each microelectronic sub-assembly having a first side and an opposing second side; a first conductive plate coupled to the first sides of the microelectronic sub-assemblies; and a second conductive plate coupled to the second sides of the microelectronic sub-assemblies. The first conductive plate and the second conductive plate comprise sockets corresponding to each of the microelectronic sub-assemblies, and each microelectronic sub-assembly comprises a first plurality of integrated circuit (IC) dies coupled on one end to a first IC die and on an opposing end to a second IC die; and a second plurality of IC dies coupled to the first IC die and to the second IC die.

Package architecture of scalable compute wall having compute bricks with vertically stacked dies

An example IC device includes a plurality of vertical transistors which may be part of memory cells, thus realizing vertical-transistor based memory. The IC device further includes a wordline, electrically continuous along a first longitudinal axis and electrically coupled to gates of a first subset of the transistors, and a control line that may be either a bitline or a plateline, electrically continuous along a second longitudinal axis and wrapping around at least portions of channel materials of a second subset of the transistors, where the first subset and the second subset have one transistor in common. At least one of the first longitudinal axis and the second longitudinal axis is not parallel to any edges or borders of the support structure, and, as a result, such a memory is referred to as 'diagonal memory.' The transistors may be hysteretic transistors and/or may be further coupled to hysteretic capacitors.

Diagonal memory with vertical transistors and wrap-around control lines

IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.

Integrated circuit devices with angled transistors formed based on angled wafers

Memory device architectures including integrated high voltage planar transistor support circuitry underlying memory cell arrays are discussed related to improving density and device performance Such memory device architectures include planar transistors having wide band gap channel materials integrated with memory cell arrays using a number of metallization layers. The metallization layers between the planar transistors and the memory cells are predominantly tungsten and the metallization layers in which the memory cells are embedded are predominantly a metal other than tungsten.

Integrated planar transistors and memory cell array architectures

Three-dimensional hysteretic memory based on semiconductor nanoribbons is disclosed. An example memory cell may include a nanoribbon-based access transistor and a capacitor coupled to the access transistor, where the capacitor at least partially wraps around the nanoribbon in which the access transistor is formed. One or both of a gate stack of the access transistor and the capacitor insulator may include a hysteretic material/arrangement. Plurality of such memory cells may be provided in a single nanoribbon, and the nanoribbon may be one of a stack of nanoribbons provided above one another over a support structure. Incorporating hysteretic memory cells in different layers above a support structure by using stacks of semiconductor nanoribbons may allow significantly increasing density of hysteretic memory cells in a memory array having a given footprint area, or conversely, significantly reducing the footprint area of the memory array with a given density of hysteretic memory cells.

Three-dimensional nanoribbon-based hysteretic memory

Described herein are transistors with front-side and back-side routing, and IC devices including such transistors. The transistor includes a channel material having a longitudinal structure and formed in a dielectric material. A source region encloses a first portion of the channel material, a gate electrode encloses a second portion of the channel material, and a drain region encloses a third portion of the channel material. Each of the source region, gate electrode, and drain region have a first face and a second face opposite the first face, the first and second faces co-planar with the faces of the dielectric material. A first contact is coupled to the first face of the source region, and a second contact is coupled to the second face of the source region.

Transistor with front-side and back-side contacts and routing

A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.

Multilevel wordline assembly for embedded DRAM

An integrated circuit includes a first conductive structure, a second conductive structure, and a first spacer and a second spacer each comprising a first dielectric material. The integrated circuit further includes a layer comprising a second dielectric material that is compositionally different from the first dielectric material. The integrated circuit further includes a first interconnect feature above and at least partially landed on the first conductive structure. In an example, the first interconnect feature is laterally between the first spacer and the second spacer. The integrated circuit further includes a second interconnect feature above and at least partially landed on the second conductive structure. In an example, the second interconnect feature is laterally between the second spacer and the layer comprising the second dielectric material.

Spacer-based self-aligned interconnect features

In one embodiment, an integrated circuit package includes: a first die having a plurality of cores, each of the plurality of cores having a local memory interface circuit to access a local portion of a dynamic random access memory (DRAM); and a second die comprising the DRAM, where at least some of the plurality of cores are directly coupled to a corresponding local portion of the DRAM by a stacking of the first die and the second die. Other embodiments are described and claimed.

Providing fine grain access to package memory

Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

Compositional engineering of Schottky diode

Stitched dies having a cooling structure are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies. A plurality of microfluidic channels is coupled to the first side of the first and second dies.

Cooling approaches for stitched dies

Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

Capacitor connections in dielectric layers

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Hillsboro, OR, United States of America

Abhishek A Sharma