International Business Machines Corporation

A James Van Norstrand, Jr

David Andrew Schroter

Dung Q Nguyen

David Allen Hrusecky

Susan Elizabeth Eisen

Kenneth Lundy Ward

Christopher M Mueller

Kevin Arthur Chiarot

Philip George Emma

Thomas R Puzak

David Scott Ray

Joshua W Knight

Barry Duane Williamson

James R Robinson

Within a processor, speculative finishes of load instructions only are tracked in a speculative finish table by maintaining an oldest load instruction of a thread in the speculative finish table after data is loaded for the oldest load instruction, wherein a particular queue index tag assigned to the oldest load instruction by an execution unit points to a particular entry in the speculative finish table, wherein the oldest load instruction is waiting to be finished dependent upon an error check code result. Responsive to a flow unit receiving the particular queue index tag with an indicator that the error check code result for data retrieved for the oldest load instruction is good, finishing the oldest load instruction in the particular entry pointed to by the queue index tag and writing an instruction tag stored in the entry for the oldest load instruction out of the speculative finish table for completion.

Efficiently managing speculative finish tracking and error handling for load instructions

An apparatus for condition register (CR) renaming and methods of using the same are implemented. In a central processing unit (CPU) having a pipelined architecture, logical operations on CR operands may be executed out-of-order using the CR renaming mechanism. Any instruction that updates the CR data has an associated instruction identifier (IID) stored in a register. Subsequent condition register logical (LCR) instructions that use data in the CR use the stored IID to determine when the CR data has been updated by the execution of the instruction corresponding to the stored IID. When an instruction causing a CR data value update finishes executing, the updated data is obtained by snooping the finish bus of the corresponding execution unit. In this way, these instructions can obtain CR data prior to completion of the preceding instructions. Because the updated CR data is available to the LCR next to execute before the updating instruction completes, deserialized execution of LCR instructions is thereby realized.

Data processing system having an apparatus for out-of-order register

One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and a rename register file. In one particular version of the invention, the method includes the steps of forwarding an instruction from the instruction cache to the sequencing unit operable to access multiple architectural registers; generating a plurality of primitive instructions responsive to the forwarded instruction in which an individual primitive instruction is operable to access an individual architectural register; and sequentially issuing the primitive instructions to move data between the data cache and the rename register file.

System for providing high performance speculative processing of complex

An apparatus for fetching instructions in a computer system is disclosed. The apparatus includes a cache circuit for holding a sub-set of main store, a buffer circuit for holding instructions fetched from the cache for dispatch to a plurality of execution units, and a branch resolution unit. A first tag associated with each instruction to be dispatched is generated that identifies the instruction while it is in process. The execution units execute dispatched instructions and provide resulting condition codes and first tag for each instruction that is completed. The branch resolution unit, fetches a not guessed instruction stream from the cache such that the not guessed instruction stream is available to the instruction buffer during the same cycle that the guess is resolved. The branch resolution unit also includes means for guessing the result of a branch instruction and means for fetching a guessed instruction stream to be fetched.

Microprocessor instruction hedge-fetching in a multiprediction branch

A computer processing system includes a first memory that stores instructions belonging to a first instruction set architecture and a second memory that stores instructions belonging to a second instruction set architecture. An instruction buffer is coupled to the first and second memories, for storing instructions that are executed by a processor unit. The system operates in one of two modes. In a first mode, instructions are fetched from the first memory into the instruction buffer according to data stored in a first branch history table. In the second mode, instructions are fetched from the second memory into the instruction buffer according to data stored in a second branch history table. The first instruction set architecture may be system level instructions and the second instruction set architecture may be millicode instructions that, for example, define a complex system level instruction and/or emulate a third instruction set architecture.

Computer processing unit employing a separate millicode branch history

Growing community of inventors

Round Rock, TX, United States of America

A James Van Norstrand, Jr