Centurion Patentors as of December 3, 2024

Welcome to December 3, 2024. This week, we aim to celebrate the centurion patentors who have reached noteworthy milestones in their fields.

A memory array is formed by creating a conductor tier on a substrate, vertical stacks of alternating sacrificial and non-sacrificial tiers, and channel-material strings. Conducting material in the lowest tier connects the channels to the conductor tier. Trenches are formed between stacks, sidewalls of the conducting material are doped, and sacrificial material is selectively etched through the trenches, preserving the doped regions.

Patent №: 12160995 (December 3, 2024) – Wakeup free approach to improve the ferroelectricity of FeRAM using a stressor layer. This disclosure describes a memory device with a semiconductor substrate, a first electrode, and a ferroelectric layer positioned between the electrode and the substrate. A stressor layer separates the electrode from the ferroelectric layer and has a higher thermal expansion coefficient than the ferroelectric layer, enhancing device performance.

Methods for staggering downlink and uplink communications involve a user equipment (UE) connecting to a base station and receiving staggering offsets for downlink and uplink communication. These offsets apply to XR, VR, or AR data streams. The UE communicates with the base station based on the provided offsets to manage data transmission effectively.