Memory device configured to alternately apply an erase voltage and an inhibit voltage

Abstract

A memory device comprises: a first memory cell, and a second memory cell different from the first memory cell, wherein the first memory cell and the second memory cell are included in same memory block; a first word line connected to the first memory cell; a second word line, different from the first word line, connected to the second memory cell; an address decoder which applies one of an erase voltage and an inhibit voltage different from the erase voltage to each of the first and second word lines; and a control logic which controls an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.The present disclosure provides a memory device for detecting a word line bridge defect through erase verification of the memory device. The memory device comprises: a first memory cell and a second memory cell; a first word line connected to the first memory cell; a second word line connected to the second memory cell; an address decoder which is configured to apply one of an erase voltage and an inhibit voltage to each of the first and second word lines; and a control logic which is configured to control an erasing operation on the memory block, using the address decoder, wherein while the erasing operation on the memory block is executed, the inhibit voltage is applied to the first word line after the erase voltage is applied, and the erase voltage is applied to the second word line after the inhibit voltage is applied.