The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2024

Filed:

Oct. 16, 2019
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Yasuhiro Hirashima, Kawasaki Kanagawa, JP;

Masaru Koyanagi, Ota Tokyo, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 7/1084 (2013.01); G11C 7/109 (2013.01); G11C 13/0002 (2013.01);
Abstract

A memory device includes a nonvolatile semiconductor memory cell array, a plurality of terminals through which control signals are received to control the memory device, an on-die termination circuit connected to at least one of the terminals and having a variable resistor, and a control circuit. The control circuit is configured to enable the on-die termination circuit in response to an enabling signal to enable the on-die termination circuit, with a resistance of the variableregistorresistorat different values depending on whether a control signal is asserted or deasserted when the enabling signal is received.


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