The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2023

Filed:

Feb. 02, 2020
Applicant:

Longitude Licensing Limited, Dublin, IE;

Inventor:

Yoshiro Riho, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2005.12); G11C 5/06 (2005.12); G11C 5/02 (2005.12); G11C 5/04 (2005.12); H01L 23/60 (2005.12); H01L 27/02 (2005.12);
U.S. Cl.
CPC ...
G11C 5/063 (2012.12); G11C 5/02 (2012.12); G11C 5/04 (2012.12); H01L 23/60 (2012.12); H01L 27/0296 (2012.12); H01L 2224/0554 (2012.12); H01L 2224/05573 (2012.12); H01L 2224/13025 (2012.12); H01L 2224/16145 (2012.12); H01L 2225/06513 (2012.12); H01L 2225/06517 (2012.12); H01L 2225/06527 (2012.12); H01L 2225/06596 (2012.12); H01L 2924/00014 (2012.12); H01L 2924/13091 (2012.12);
Abstract

A method of testing a semiconductor device includes providing a first wafer that includes a first surface, a second surface that is allocated at an opposite side of the first surface, a first electrode penetrating the first wafer from the first surface to the second surface, and a pad formed on the first surface and coupled electrically with the first electrode, providing a second wafer that includes a second electrode penetrating the second wafer, stacking the first wafer onto the second wafer to connect the first electrode with the second electrode such that the second surface of the first wafer faces the second wafer, probing a needle to the pad, and supplying, in such a state that the first wafer is stacked on the second wafer, a test signal to the first electrode to input the test signal into the second wafer via the first electrode and the second electrode.


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