The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 13, 2021

Filed:

May. 19, 2019
Applicants:

Kunshan New Flat Panel Display Technology Center Co., Ltd., Kunshan, CN;

Kunshan Go-visionox Opto-electronics Co., Ltd., Kunshan, CN;

Inventors:

Siming Hu, Kunshan, CN;

Hui Zhu, Kunshan, CN;

Xiuqi Huang, Kunshan, CN;

Xiaoyu Gao, Kunshan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2005.12); G09G 3/3266 (2015.12); G09G 3/3291 (2015.12); G11C 19/28 (2005.12);
U.S. Cl.
CPC ...
G09G 3/3266 (2012.12); G09G 3/3291 (2012.12); G11C 19/28 (2012.12); G09G 2310/0283 (2012.12); G09G 2310/0286 (2012.12); G09G 2310/08 (2012.12); G09G 2320/0219 (2012.12); G09G 2330/021 (2012.12);
Abstract

The present invention provides a scanning driver and an organic light-emitting display using the same. The scanning driver comprises a plurality of cascaded structures receiving signals from a first timing clock line (CK) and a second timing clock line (CK) with opposite phases, the cascaded structures successively generating output signals (i.e., scanning signals), wherein each of the cascaded structures comprises: a first transistor, connected to a starting signal line or to a scanning output line of a previous cascaded structure; a second transistor, connected to the second timing clock line and to the scanning output line; a third transistor connected to a high-level power supply VGH; a fourth transistor, connected to a low-level power supply VGL and to an output terminal of the third transistor; a fifth transistor, connected to a high-level power supply VGH and to a scanning output line; and a first capacitor, connected between an output terminal of the first transistor and the scanning output line. Arranging a first capacitor Cbetween the output terminal of Mand the scanning output line prevents slight-ON of Mthus reducing the reverse current at the scanning driver and reducing the power consumption.


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