The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 30, 2020
Filed:
Dec. 08, 2013
Applicant:
Conversant Intellectual Property Management Inc., Ottawa, CA;
Inventors:
Young-Hoon Oh, Gyeonggi-do, KR;
Kwang-Myoung Rho, Kyoungki-do, KR;
Assignee:
Conversant Intellectual Property Management Inc., Ottawa, CA;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2005.12); G11C 11/4076 (2005.12); G11C 7/10 (2005.12); G11C 29/02 (2005.12); G11C 7/22 (2005.12); G11C 11/401 (2005.12);
U.S. Cl.
CPC ...
G11C 11/4076 (2012.12); G11C 7/1051 (2012.12); G11C 7/1069 (2012.12); G11C 7/22 (2012.12); G11C 7/222 (2012.12); G11C 29/02 (2012.12); G11C 29/023 (2012.12); G11C 29/028 (2012.12); G11C 11/401 (2012.12); G11C 2207/2254 (2012.12);
Abstract
A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a calibration controller for controlling the predetermined delay time of the variable delay in response to output AC parameters.