The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 17, 2020

Filed:

Feb. 03, 2016
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Naoya Tokiwa, Fujisawa, JP;

Hideo Mukai, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2005.12); G11C 16/04 (2005.12); G11C 8/08 (2005.12); G11C 16/08 (2005.12); G11C 16/30 (2005.12); G11C 29/02 (2005.12); H01L 27/11578 (2016.12); H01L 27/11582 (2016.12); G11C 29/12 (2005.12);
U.S. Cl.
CPC ...
G11C 16/0483 (2012.12); G11C 8/08 (2012.12); G11C 16/08 (2012.12); G11C 16/30 (2012.12); G11C 29/028 (2012.12); H01L 27/11578 (2012.12); H01L 27/11582 (2012.12); G11C 2029/1202 (2012.12);
Abstract

A three-dimensionally stacked nonvolatile semiconductor memory of an aspect of the present invention including conductive layers stacked on a semiconductor substrate in such a manner as to be insulated from one another, a bit line which is disposed on the stacked conductive layers, a semiconductor column which extends through the stacked conductive layers, word lines for which the stacked conductive layers except for the uppermost and lowermost conductive layers are used and which have a plate-like planar shape, memory cells provided at intersections of the word lines and the semiconductor column, a register circuit which has information to supply a potential suitable for each of the word lines, and a potential control circuit which reads the information retained in the register circuit in accordance with an input address signal of a word line and which supplies a potential suitable for the word line corresponding to the address signal.


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