The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2020
Filed:
Jan. 28, 2019
Renesas Electronics Corporation, Tokyo, JP;
Koji Nii, Tokyo, JP;
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Abstract
A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I) consists of a NMOS transistor (N) and a PMOS transistor (P), and an inverter (I) consists of a NMOS transistor (N) and a PMOS transistor (P). The inverters (II) are subjected to cross section. The NMOS transistor (N) is formed within a P well region (PW), and the NMOS transistor (N) is formed within a P well region (PW). The P well regions (PWPW) are oppositely disposed with an N well region (NW) interposed therebetween.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile