The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2020
Filed:
Jan. 28, 2019
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventor:
Koji Nii, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2005.12); G11C 5/00 (2005.12);
U.S. Cl.
CPC ...
G11C 11/4125 (2012.12); G11C 5/005 (2012.12);
Abstract
A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I) consists of a NMOS transistor (N) and a PMOS transistor (P), and an inverter (I) consists of a NMOS transistor (N) and a PMOS transistor (P). The inverters (II) are subjected to cross section. The NMOS transistor (N) is formed within a P well region (PW), and the NMOS transistor (N) is formed within a P well region (PW). The P well regions (PWPW) are oppositely disposed with an N well region (NW) interposed therebetween.