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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US RE46636 B1

PDFFull Text
Date of Patent:
Dec. 11, 2017

Filed:

Aug. 25, 2015

Nonvolatile memory device, nonvolatile memory device group, and manufacturing method thereof

Applicant:

Sony Corporation, Tokyo, JP;

Inventors:

Jun Sumino, Kanagawa, JP;

Motonari Honda, Kanagawa, JP;

Assignee:

SONY CORPORATION, Tokyo, JP;

Attorney:

Dentons US LLP

Primary Examiner:

James Menefee

Int. Cl.
CPC ...
H01L 29/06 (2005.12); H01L 21/20 (2005.12); H01L 45/00 (2005.12); H01L 27/22 (2005.12); H01L 27/24 (2005.12); H01L 43/08 (2005.12); H01L 43/10 (2005.12);
U.S. Cl.
CPC ...
H01L 45/1246 (2012.12); H01L 27/228 (2012.12); H01L 27/2436 (2012.12); H01L 27/2472 (2012.12); H01L 43/08 (2012.12); H01L 43/10 (2012.12); H01L 45/06 (2012.12); H01L 45/085 (2012.12); H01L 45/122 (2012.12); H01L 45/1206 (2012.12); H01L 45/1226 (2012.12); H01L 45/1266 (2012.12); H01L 45/142 (2012.12); H01L 45/143 (2012.12); H01L 45/144 (2012.12); H01L 45/146 (2012.12); H01L 45/147 (2012.12); H01L 45/16 (2012.12); H01L 45/1683 (2012.12);
Abstract

A nonvolatile memory device group includes: (A) a first insulating layer; (B) a second insulating layer that has a first concavity and a second concavity communicating with the first concavity and having a width larger than that of the first concavity and that is disposed on the first insulating layer; (C) a plurality of electrodes that are disposed in the first insulating layer and the top surface of which is exposed from the bottom surface of the first concavity; (D) an information storage layer that is formed on the side walls and the bottom surfaces of the first concavity and the second concavity; and (E) a conductive material layer that is filled in a space surrounded with the information storage layer in the second concavity.

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