The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 2016

Filed:

May. 29, 2014
Applicant:

Renesas Electronics Corporation, Kanagawa, JP;

Inventors:

Tsutomu Wada, Higashiyamato, JP;

Masachika Masuda, Tokorozawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2005.12);
U.S. Cl.
CPC ...
H01L 21/44 (2012.12); H01L 2924/01079 (2012.12);
Abstract

For the manufacturing of semiconductor devices, in which multiple semiconductor chips which are mounted on a wiring substrate are processed for block molding and thereafter the wiring substrate is diced into individual resin-molded semiconductor devices, disclosed herein is a technique for easily determining the position of each resin-molded semiconductor device in its former state on the wiring substrate even after the dicing process. The processing steps include implementing the block molding with resin for multiple semiconductor chips mounted on a wiring substrate and thereafter dicing the wiring substrate into individual resin-molded semiconductor devices, with the substrate dicing step being preceded by a step of appending an address information pattern to each of the resin-molded semiconductor devices.


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