The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 19, 2012
Filed:
Aug. 04, 2009
Byoung Ho Lim, Kyongsangbuk-do, KR;
Hee Chun Boo, Legal Representative, Kyongsangbuk-do, KR;
Hyun Sik Seo, Gyeonggi-do, KR;
Heung Lyul Cho, Gyeonggi-do, KR;
Hong Sik Kim, Seoul, KR;
Byoung Ho Lim, Kyongsangbuk-do, KR;
Hee Chun Boo, legal representative, Kyongsangbuk-do, KR;
Hyun Sik Seo, Gyeonggi-do, KR;
Heung Lyul Cho, Gyeonggi-do, KR;
Hong Sik Kim, Seoul, KR;
LG Display Co., Ltd., Seoul, KR;
Abstract
A thin film transistor array substrate device includes a gate line formed on a substrate, a data line crossing the gate line with a gate insulating pattern position therebetween, a thin film transistor at a crossing of the gate line and the data line, a pixel electrode formed at a pixel region defined by the crossing of the gate line and the data line and connected to the thin film transistor, a gate pad part having a lower gate pad electrode connected to the gate line and an upper gate pad electrode connected to the lower gate pad electrode, a data pad part having a lower data pad electrode connected to the date line and an upper data pad electrode connected to the lower data pad electrode, and a passivation film pattern formed at a region besides the region including the pixel electrode, the upper data pad electrode, and the upper gate pad electrode, wherein the pixel electrode is formed on the gate insulating pattern of the pixel region exposed by the passivation film pattern.