Method and system for displaying an analog image by a digital display device

Abstract

A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.A system and method for displaying an analog source image by a digital display unit. A converter circuit generates a plurality of digital source image elements from an analog source image based upon a sampling clock signal synchronized with a time reference signal associated with the analog source image. A scaler unit receives the digital source image elements in accordance with a first clock signal, scales the source image elements independently in both vertical and horizontal directions to form destination image elements, and provides the destination image elements to the display unit in accordance with a second clock signal. The first clock signal and the second clock signal are arranged such that a source frame rate and a destination frame rate are substantially equal.