The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2006

Filed:

Feb. 12, 2003
Applicants:

Toru Morikawa, Mino, JP;

Nobuo Higaki, Kobe, JP;

Akira Miyoshi, Hirakata, JP;

Keizo Sumida, Hirakata, JP;

Inventors:

Toru Morikawa, Mino, JP;

Nobuo Higaki, Kobe, JP;

Akira Miyoshi, Hirakata, JP;

Keizo Sumida, Hirakata, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/302 (2005.12); G06F 7/38 (2005.12);
U.S. Cl.
CPC ...
Abstract

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction 'MCSST D' is decoded, the sum-product result registeroutputs its held value to the path P. The comparatorcompares the magnitude of the held value of the sum-product result registerwith the coded 32-bit integer '0x0000_00FF'. The polarity judging unitjudges whether the eighth bit of the value held by the sum-product result registeris “ON”. The multiplexeroutputs one of the maximum value “0x0000_00FF” generated by the constant generator, the zero value “0x0000_0000” generated by the zero generator, and the held value of the sum-product result registerto the data bus


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