Method for fabricating a silicon-on-insulator voltage multiplier

Abstract

The present invention provides a method for fabricating a silicon-on-insulator voltage multiplier. The method comprises the steps of: forming a first silicon layer having a first concentration of a first dopant with a first polarity on a silicon wafer having a second concentration of a second dopant with a second polarity opposite the first polarity to create a diode junction; forming a second silicon layer on the first silicon layer, the second silicon layer having a third concentration of a third dopant having the first polarity, where the third concentration is greater than the first concentration of the first dopant; forming a silicon dioxide layer on the second silicon layer by thermal oxidation; bonding an insulating substrate to the silicon dioxide layer to create a bonded wafer, where the insulating substrate is selected from the group consisting of quartz, glass, sapphire, and silicon dioxide on silicon; thinning the silicon wafer to form a thinned silicon layer; etching the bonded wafer to form a plurality of separate diodes having sloped sidewalls and to expose selected regions of the insulating substrate; forming an insulating silicon layer on the selected regions of the insulating substrate and on the separate diodes; exposing selected regions of the thinned silicon layer and regions of the second silicon layer of each of the diodes; and forming metal interconnects between the exposed selected regions of the thinned silicon layer of one of the diodes with the silicon layer of another of the diodes.