The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 1995

Filed:

Feb. 11, 1991
Applicant:
Inventor:

Gary S Borgen, Port Hueneme, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L / ;
U.S. Cl.
CPC ...
380-4 ; 380-9 ; 380 21 ; 380 49 ; 380 50 ; 395425 ;
Abstract

A nonvolatile memory system is disclosed which will store a key or digital word for a period of time of approximately three years with minimum power consumption. The nonvolatile memory system includes a nonvolatile static random access memory for receiving and storing a key word from a loader, and a nonvolatile memory sequence control circuit which provides logic signals for controlling read and write operations of the nonvolatile static RAM, as well as logic signals to allow for transfer or down loading of the key word from the loader to the RAM. In addition, the nonvolatile memory sequence control circuit provides logic signals to interface with an encryption device which allows the key word to be transferrred or up loaded from the nonvolatile static RAM to the encryption device and logic signals for storing the key word in a nonvolatile electrically erasable programmable read only memory (PROM) and then bringing the nonvolatile static RAM to a low power standby state. An erasable PROM (EPROM) is used to control the sequencing of operations within the nonvolatile static RAM with addressing for the EPROM being provided by the nonvolatile memory sequence control circuit. The EPROM and the nonvolatile memory sequence control circuit may be also brought to a low power standby state by a power control signal provided by the memory sequence control circuit.


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