Automated universal array

Abstract

A large scale integrated semiconductor array consisting of a layout of predefined uncommitted active circuit components such as transistors which provide for logic function implementation and chip interfacing along with a region of passive circuit components used for signal and power routing. The various components are adapted to be interconnected on a single level which renders it particularly adaptable for automated layout techniques. The array is comprised of a plurality of rows of identical basic internal cells which are symmetrical and separated by an inner roadbed area consisting of at least three, but preferably five, vertical tunnel patterns, each of which is adapted to accommodate three horizontal wiring channels overhead for providing horizontal signal routing. Interconnection and vertical signal routing between cell rows can be made through a feedthrough in each internal cell and connection to selective vertical tunnels without touching the overhead horizontal wiring channels which provide horizontal signal routing. A side peripheral roadbed area adjoins the cell rows and inner roadbed area and consists of an alternating pattern of horizontal and vertical tunnels which permit interfacing with a bordering arrangement of peripheral cells consisting of basic peripheral cells and special purpose cells as well as providing coupling to a pair of common power busses which are located on the outer perimeter of the array.