The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Jan. 14, 2015
Applicant:

Super Micro Computer, Inc., San Jose, CA (US);

Inventors:

Richard S. Chen, San Jose, CA (US);

Andy Chen, San Jose, CA (US);

Jonathan M. Lee, Fremont, CA (US);

Wenjuan Yu, San Jose, CA (US);

Assignee:

SUPER MICRO COMPUTER, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/20 (2006.01);
U.S. Cl.
CPC ...
H05K 7/20727 (2013.01); H05K 7/20172 (2013.01);
Abstract

A circuit layout includes two or more high performance processing nodes that are cooled by a cooling fan. The cooling fan resides in a cooling fan assembly that relies on principles of aerodynamics to maximize airflow. The cooling fan assembly is coupled to the opposite side of a backplane to which the circuit layout is mounted. The backplane includes large ventilation holes to permit the cooling fan to induce significantly more airflow across the circuit layout than possible with conventional designs. At least one advantage of the approaches discussed herein is circuit layouts can be constructed to meet the competing objectives of high node performance and high node density. Accordingly, data centers can be built that offer high performance computing without requiring a significant increase in physical real estate.


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