The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2018
Filed:
Mar. 25, 2016
Applicant:
Multek Technologies Limited, San Jose, CA (US);
Inventors:
Assignee:
Multek Technologies Limited, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/03 (2006.01); H05K 3/04 (2006.01); H05K 1/18 (2006.01); H05K 3/46 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/048 (2013.01); H05K 1/183 (2013.01); H05K 1/036 (2013.01); H05K 3/0035 (2013.01); H05K 3/0044 (2013.01); H05K 3/4697 (2013.01); H05K 2201/0187 (2013.01); H05K 2201/0989 (2013.01); H05K 2201/09109 (2013.01); H05K 2203/0228 (2013.01); H05K 2203/1383 (2013.01);
Abstract
A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes a recessed cavity, a bottom perimeter of which is formed by a photo definable, or photo imageable, polymer structure, such as a solder mask frame, and a protective film. The solder mask frame and protective film protect inner core circuitry at the bottom of the cavity during the fabrication process, as well as enable the use of regular flow prepreg in the laminated stack.