The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Jul. 07, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Eskinder Hailu, Cary, NC (US);

Bupesh Pandita, Raleigh, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/085 (2006.01); G04F 10/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/085 (2013.01); G04F 10/005 (2013.01);
Abstract

Aspects of the disclosure are directed to generating a quadrature clock signal from an in-phase clock signal. In accordance with one aspect, a delay locked loop (DLL), including a first pulse to digital converter (PDC) to generate a first pulse width measurement, wherein the first pulse width measurement includes a first sign and a first magnitude; a second pulse to digital converter (PDC) to generate a second pulse width measurement, wherein the second pulse width measurement includes a second sign and a second magnitude; a digital loop filter coupled to the first PDC and the second PDC, the digital loop filter to generate a filtered comparison output based on the first pulse width measurement and the second pulse width measurement; and a first delay generation block to generate a quadrature clock signal based on the filtered comparison output and an in-phase clock signal.


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