The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

May. 12, 2017
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Shintaro Harada, Kanagawa, JP;

Munehiro Kozuma, Kanagawa, JP;

Yoshiyuki Kurokawa, Kanagawa, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 27/12 (2006.01); H03K 19/00 (2006.01); H01L 29/786 (2006.01); G11C 19/28 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0013 (2013.01); G11C 19/28 (2013.01); H01L 27/124 (2013.01); H01L 27/1207 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); H01L 29/7851 (2013.01); H01L 29/7869 (2013.01); H03K 19/1778 (2013.01);
Abstract

Provided is a semiconductor device in which leakage current due to miniaturization of a semiconductor element is reduced and delay at a time of context switch of a multi-context PLD is reduced. A first transistor and a second transistor included in a charge retention circuit functioning as a configuration memory each include an oxide semiconductor in a semiconductor layer serving as a channel formation region. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is connected to a switch for context switch. In the switch used for context switch, electrostatic capacitance on an input side to which the one of the source and the drain of the second transistor is connected is larger than electrostatic capacitance on an output side.


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