The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2018
Filed:
May. 23, 2014
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Wenjun Su, San Diego, CA (US);
Chulkyu Lee, San Diego, CA (US);
Le Zhang, Shanghai, CN;
Guangming Yin, Newport Coast, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/00 (2006.01); H02M 3/07 (2006.01); H03K 5/159 (2006.01); H03K 3/011 (2006.01); H03K 17/14 (2006.01); H03K 19/003 (2006.01); G05F 3/26 (2006.01);
U.S. Cl.
CPC ...
H03K 3/011 (2013.01); G05F 1/00 (2013.01); G05F 3/262 (2013.01); H02M 3/07 (2013.01); H03K 5/159 (2013.01); H03K 17/145 (2013.01); H03K 19/00384 (2013.01); H03K 2217/0018 (2013.01);
Abstract
A feed-forward bias circuit biases body bias terminals of transistors of another circuit to compensate for PVT variations in the other circuit. In some aspects, the feed-forward bias circuit compensates for transistor process corners in a circuit by enabling the generation of different bias signals under different corner conditions. In some implementations, the feed-forward bias circuit is used to bias a delay circuit so that the delay circuit exhibits relatively constant delay characteristics over different PVT conditions.