The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Jul. 25, 2013
Applicant:

Hewlett-packard Development Company, L.p., Houston, TX (US);

Inventors:

Si-Ty Lam, Palo Alto, CA (US);

Xia Sheng, Palo Alto, CA (US);

Richard H. Henze, Palo Alto, CA (US);

Zhang-Lin Zhou, San Diego, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1273 (2013.01); H01L 27/2463 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/145 (2013.01); H01L 45/146 (2013.01); H01L 45/16 (2013.01); H01L 45/1608 (2013.01); H01L 45/1675 (2013.01);
Abstract

A resistive memory device includes a bottom electrode and a top electrode sandwiching a switching layer. The device also includes a field enhancement (FE) feature that extends from the bottom electrode either into the switching layer or is covered by switching layer and that is to enhance an electric field generated by the two electrodes to thereby confine a switching area of the device at the FE feature. The device further includes a planar interlayer dielectric surrounding the device, for supporting the top electrode. A method of making a resistive memory device, employing in-situ vacuum deposition of all layers, is also provided.


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