The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Nov. 18, 2016
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Satoshi Eguchi, Ibaraki, JP;

Hitoshi Matsuura, Ibaraki, JP;

Yuya Abiko, Ibaraki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 21/324 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 29/06 (2006.01); H01L 29/32 (2006.01); H01L 29/40 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7396 (2013.01); H01L 21/265 (2013.01); H01L 21/324 (2013.01); H01L 29/0634 (2013.01); H01L 29/0688 (2013.01); H01L 29/32 (2013.01); H01L 29/404 (2013.01); H01L 29/6634 (2013.01); H01L 29/66333 (2013.01); H01L 29/1095 (2013.01);
Abstract

Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region.


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