The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Oct. 09, 2015
Applicant:

Western Digital Technologies, Inc., Irvine, CA (US);

Inventor:

Daniel R. Shepard, North Hampton, NH (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/22 (2006.01); H01L 43/10 (2006.01); H01L 43/06 (2006.01); H01L 43/04 (2006.01); H01L 27/24 (2006.01); G11C 11/16 (2006.01); H01L 27/10 (2006.01);
U.S. Cl.
CPC ...
H01L 27/228 (2013.01); G11C 11/1659 (2013.01); H01L 27/10 (2013.01); H01L 27/2463 (2013.01); H01L 43/04 (2013.01); H01L 43/06 (2013.01); H01L 43/10 (2013.01);
Abstract

Embodiments of the present disclosure generally relate to data storage systems, and more particularly, to a SHE-MRAM device. The SHE-MRAM device includes a memory cell array having a plurality of first leads, a plurality of second leads, and a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads. The second leads are made of a material having large spin orbit interactions and high electrical resistivity. The SHE-MRAM device further includes a periphery circuitry having multiple pairs of transistors. The multiple pairs of transistors reduce the length a current has to flow through a second lead of the plurality of second leads. By limiting the distance a current can flow through the second lead, applying excessive voltage to the second lead is avoided.


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