The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2018
Filed:
May. 16, 2016
Yong-hoon Son, Yongin-si, KR;
Kyung-hyun Kim, Seoul, KR;
Byeong-ju Kim, Hwaseong-si, KR;
Phil-ouk Nam, Suwon-si, KR;
Kwang Chul Park, Suwon-si, KR;
Yeon-sil Sohn, Yongin-si, KR;
Jin-i Lee, Hwaseong-si, KR;
Jong-heun Lim, Hwaseong-si, KR;
Won-bong Jung, Seoul, KR;
Kohji Kanamori, Seoul, KR;
Yong-Hoon Son, Yongin-si, KR;
Kyung-Hyun Kim, Seoul, KR;
Byeong-Ju Kim, Hwaseong-si, KR;
Phil-Ouk Nam, Suwon-si, KR;
Kwang Chul Park, Suwon-si, KR;
Yeon-Sil Sohn, Yongin-si, KR;
Jin-I Lee, Hwaseong-si, KR;
Jong-Heun Lim, Hwaseong-si, KR;
Won-Bong Jung, Seoul, KR;
Kohji Kanamori, Seoul, KR;
Abstract
A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.