The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

May. 11, 2015
Applicants:

Gukhyon Yon, Hwaseong-si, KR;

Dongwoo Kim, Incheon, KR;

Kihyun Hwang, Seongnam-si, KR;

Dongkyum Kim, Suwon-si, KR;

Dongchul Yoo, Seongnam-si, KR;

Inventors:

Gukhyon Yon, Hwaseong-si, KR;

Dongwoo Kim, Incheon, KR;

Kihyun Hwang, Seongnam-si, KR;

Dongkyum Kim, Suwon-si, KR;

Dongchul Yoo, Seongnam-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); H01L 27/24 (2006.01); H01L 27/11578 (2017.01); H01L 27/11556 (2017.01); H01L 27/11575 (2017.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/11556 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01); H01L 27/11578 (2013.01); H01L 27/249 (2013.01); H01L 27/2436 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/1226 (2013.01); H01L 45/144 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A three-dimensional semiconductor memory device includes a peripheral circuit structure on a substrate, a horizontal active layer on the peripheral circuit structure, stacks provided on the horizontal active layer to include a plurality of electrodes, a vertical structure vertically penetrating the stacks, a common source region between ones of the stacks and in the horizontal active layer, and pick-up regions in the horizontal active layer. The horizontal active layer includes first, second, and third active semiconductor layers sequentially stacked on the peripheral circuit structure. The first and third active semiconductor layers are doped to have high and low impurity concentrations, respectively, and the second active semiconductor layer includes an impurity diffusion restraining material.


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