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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9997510 B1

PDFFull Text
Date of Patent:
Jun. 12, 2018

Filed:

Sep. 09, 2015

Semiconductor device layout structure

Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Chi-Li Tu, Cyonglin Township, TW;

Ching-Wen Wang, Hemei Township, TW;

Karuna Nidhi, Patna, IN;

Assignee:

VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION, Hsinchu, TW;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Yu Chen

Assistant Examiner:

Pauline Vu

Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/735 (2006.01); H01L 29/866 (2006.01); H01L 29/872 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0255 (2013.01); H01L 27/0248 (2013.01); H01L 27/0259 (2013.01); H01L 27/0262 (2013.01); H01L 27/0274 (2013.01); H01L 27/0277 (2013.01); H01L 27/067 (2013.01); H01L 28/20 (2013.01); H01L 29/0642 (2013.01); H01L 29/0646 (2013.01); H01L 29/0649 (2013.01); H01L 29/0808 (2013.01); H01L 29/0821 (2013.01); H01L 29/1008 (2013.01); H01L 29/735 (2013.01); H01L 29/866 (2013.01); H01L 29/872 (2013.01); H01L 27/0207 (2013.01);
Abstract

The invention provides a semiconductor device layout structure disposed in an active region. The semiconductor device layout structure includes a first well region having a first conduction type. A second well region having a second conduction type opposite the first conduction type is disposed adjacent to and enclosing the first well region. A first doped region having the second conduction type is disposed within the first well region. A second doped region having the second conduction type is disposed within the first well region. The second doped region is separated from and surrounds the first doped region. A third doped region having the second conduction type is disposed within the second well region.

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