The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Jul. 11, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Ki Ho Bae, Seoul, KR;

Jaeseok Kim, Seoul, KR;

Hoyoung Kim, Seongnam-si, KR;

Boun Yoon, Seoul, KR;

KyungTae Lee, Seoul, KR;

Kwansung Kim, Yongin-si, KR;

Eunji Park, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 21/321 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823475 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76897 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 23/5226 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming on a substrate gate electrodes extending in a first direction and spaced apart from each other in a second direction, forming capping patterns on the gate electrodes, forming interlayer dielectric layer filling spaces between adjacent gate electrodes, forming a hardmask on the interlayer dielectric layer with an opening selectively exposing second to fourth capping patterns, using the hardmask as an etch mask to form holes in the interlayer dielectric layer between the second and third gate electrodes and between the third and fourth gate electrodes, forming a barrier layer and a conductive layer in the holes, performing a first planarization to expose the hardmask, performing a second planarization to expose a portion of the barrier layer covering the second to fourth capping patterns, and performing a third planarization to completely expose the first to fourth capping patterns.


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