The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Jan. 08, 2016
Applicant:

Tesla, Inc., Palo Alto, CA (US);

Inventors:

Mehrdad M. Moslehi, Milpitas, CA (US);

David Xuan-Qi Wang, Milpitas, CA (US);

Assignee:

Tesla, Inc., Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01T 23/00 (2006.01); H01L 21/683 (2006.01); G03F 7/20 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/3065 (2006.01); H02N 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/6833 (2013.01); G03F 7/70708 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/02255 (2013.01); H01L 21/02271 (2013.01); H01L 21/3065 (2013.01); H01L 21/683 (2013.01); H01L 21/6831 (2013.01); H01L 21/76251 (2013.01); H01L 21/76275 (2013.01); H01L 21/76281 (2013.01); H01L 21/76879 (2013.01); H02N 13/00 (2013.01); Y02P 80/30 (2015.11);
Abstract

In one embodiment, there is provided a carrier comprising a top semiconductor layer having isolated positive electrode regions and isolated negative electrode regions separated by a frontside trench through the top semiconductor layer extending at least to an underlying insulating layer positioned between the top semiconductor layer and a bottom semiconductor layer. A dielectric layer covers the top exposed surfaces of the carrier. Backside trenches through the bottom semiconductor layer extending at least to the insulating layer form isolated backside regions corresponding to the frontside positive and negative electrode regions. Backside contacts positioned on the bottom semiconductor layer and coupled to the positive and negative electrode regions allow for the electric charging of the frontside electrode regions.


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