The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Aug. 06, 2012
Applicant:

Srinivasa Raghavan Sridhara, Plano, TX (US);

Inventor:

Srinivasa Raghavan Sridhara, Plano, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/00 (2006.01); G11C 29/50 (2006.01); G11C 11/41 (2006.01);
U.S. Cl.
CPC ...
G11C 29/00 (2013.01); G11C 29/50016 (2013.01); G11C 11/41 (2013.01);
Abstract

An embodiment of the invention discloses a method for testing the retention mode of an array of SRAM cells. A data pattern is written to the array. After the data pattern is written, a retention circuit is enabled for a period of time that drops the voltage on a supply line. During this period of time, a first current is drawn from the supply line by sources internal (i.e. leakage current) to the array. Also during this time period, current is drawn from the supply line by a discharge circuit. The second current is provided to shorten the time required to test the retention mode of the array. After the period of time has expired, the retention mode and the discharge circuit are disabled and the data pattern is read from the array and compared to the data pattern written to the array.


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