The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2018
Filed:
Feb. 24, 2017
Toshiba Memory Corporation, Minato-ku, Tokyo, JP;
SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;
Yutaka Shirai, Seongnam, KR;
Naoki Shimizu, Seoul, KR;
Kenji Tsuchida, Seoul, KR;
Yoji Watanabe, Yokohama, JP;
Ji Hyae Bae, Icheon-si, KR;
Yong Ho Kim, Namyangju-si, KR;
TOSHIBA MEMORY CORPORATION, Tokyo, JP;
SK HYNIX INC., Icheon-si, Gyeonggi-Do, KR;
Abstract
A nonvolatile random access memory including a memory cell array including banks, each bank including rows; an address latch circuit; and a control circuit receiving a first set of signals including a precharge command and a first row address, and a second set of signals including an active command and a second row address. The control circuit executes a first operation in which one of the banks is deactivated when the first set of signals is loaded, executes a second operation in which the first row address is loaded when the first set of signals is loaded, and executes a third operation in which at least one of the rows in the bank is selected and activated based on the second row address when the second set of signals is loaded after the first set of signals.