The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 12, 2018

Filed:

Mar. 29, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Chulmin Jung, San Diego, CA (US);

Po-Hung Chen, San Diego, CA (US);

Fahad Ahmed, San Diego, CA (US);

Changho Jung, San Diego, CA (US);

Sei Seung Yoon, San Diego, CA (US);

David Li, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/08 (2006.01); G11C 5/14 (2006.01); H03K 19/0185 (2006.01); G11C 8/10 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 5/147 (2013.01); G11C 7/12 (2013.01); G11C 8/10 (2013.01); H03K 19/018528 (2013.01);
Abstract

A circuit including an output node and a cross-coupled pair of semiconductor devices configured to provide, at the output node, an output signal in a second voltage domain based on an input signal in a first voltage domain is described herein. The circuit further includes a pull-up assist circuit coupled to the output node; and a look-ahead circuit coupled to the pull-up assist circuit, wherein the look-ahead circuit is configured to cause the pull-up assist circuit to assist in increasing a voltage level at the output node when there is a decrease in a voltage level of an inverted output signal in the second voltage domain from a high voltage level of the second voltage domain to a low voltage level of the second voltage domain.


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